1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 32 $(flavor_dts_file-157A_DK1) \ 33 $(flavor_dts_file-157C_DHCOM_PDK2) \ 34 $(flavor_dts_file-157C_DK2) \ 35 $(flavor_dts_file-157C_ED1) \ 36 $(flavor_dts_file-157C_EV1) 37 38flavorlist-MP13 = $(flavor_dts_file-135F_DK) 39 40ifneq ($(PLATFORM_FLAVOR),) 41ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 42$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 43endif 44CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 45endif 46CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 47 48ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 49$(call force,CFG_STM32_CRYP,n) 50endif 51 52ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 53$(call force,CFG_STM32MP13,y) 54endif 55 56ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 57$(call force,CFG_STM32MP15,y) 58endif 59 60# CFG_STM32MP1x switches are exclusive. 61# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 62# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 63ifeq ($(CFG_STM32MP13),y) 64$(call force,CFG_STM32MP15,n) 65else 66$(call force,CFG_STM32MP15,y) 67$(call force,CFG_STM32MP13,n) 68endif 69ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 70$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 71endif 72ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 73$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 74endif 75 76include core/arch/arm/cpu/cortex-a7.mk 77 78$(call force,CFG_DRIVERS_CLK,y) 79$(call force,CFG_DRIVERS_CLK_DT,y) 80$(call force,CFG_GIC,y) 81$(call force,CFG_INIT_CNTVOFF,y) 82$(call force,CFG_PSCI_ARM32,y) 83$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 84$(call force,CFG_SM_PLATFORM_HANDLER,y) 85$(call force,CFG_STM32_SHARED_IO,y) 86 87ifeq ($(CFG_STM32MP13),y) 88$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 89$(call force,CFG_CORE_RESERVED_SHM,n) 90$(call force,CFG_DRIVERS_CLK_FIXED,y) 91$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 92$(call force,CFG_STM32_GPIO,y) 93$(call force,CFG_STM32_RNG,n) 94$(call force,CFG_STM32MP_CLK_CORE,y) 95$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 96$(call force,CFG_STM32MP13_CLK,y) 97$(call force,CFG_TEE_CORE_NB_CORE,1) 98$(call force,CFG_WITH_NSEC_GPIOS,n) 99CFG_EXTERNAL_DT ?= n 100CFG_STM32MP_OPP_COUNT ?= 2 101CFG_WITH_PAGER ?= n 102endif # CFG_STM32MP13 103 104ifeq ($(CFG_STM32MP15),y) 105$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 106$(call force,CFG_DRIVERS_CLK_FIXED,n) 107$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 108$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 109$(call force,CFG_STM32MP15_CLK,y) 110CFG_CORE_RESERVED_SHM ?= y 111CFG_EXTERNAL_DT ?= y 112CFG_STM32_BSEC_SIP ?= y 113CFG_TEE_CORE_NB_CORE ?= 2 114CFG_WITH_PAGER ?= y 115endif # CFG_STM32MP15 116 117CFG_WITH_LPAE ?= y 118CFG_WITH_SOFTWARE_PRNG ?= y 119CFG_MMAP_REGIONS ?= 23 120CFG_DTB_MAX_SIZE ?= (256 * 1024) 121CFG_CORE_ASLR ?= n 122 123ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 124CFG_TZDRAM_START ?= 0xde000000 125CFG_DRAM_SIZE ?= 0x20000000 126endif 127 128CFG_DRAM_BASE ?= 0xc0000000 129CFG_DRAM_SIZE ?= 0x40000000 130CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 131CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 132ifeq ($(CFG_STM32MP15),y) 133CFG_TZDRAM_START ?= 0xfe000000 134ifeq ($(CFG_CORE_RESERVED_SHM),y) 135CFG_TZDRAM_SIZE ?= 0x01e00000 136else 137CFG_TZDRAM_SIZE ?= 0x02000000 138endif 139CFG_TZSRAM_START ?= 0x2ffc0000 140CFG_TZSRAM_SIZE ?= 0x0003f000 141ifeq ($(CFG_CORE_RESERVED_SHM),y) 142CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 143CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 144endif 145else 146CFG_TZDRAM_SIZE ?= 0x02000000 147CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 148endif #CFG_STM32MP15 149 150CFG_STM32_BSEC ?= y 151CFG_STM32_CRYP ?= y 152CFG_STM32_ETZPC ?= y 153CFG_STM32_GPIO ?= y 154CFG_STM32_I2C ?= y 155CFG_STM32_IWDG ?= y 156CFG_STM32_RNG ?= y 157CFG_STM32_RSTCTRL ?= y 158CFG_STM32_TAMP ?= y 159CFG_STM32_UART ?= y 160CFG_STPMIC1 ?= y 161CFG_TZC400 ?= y 162 163ifeq ($(CFG_STPMIC1),y) 164$(call force,CFG_STM32_I2C,y) 165$(call force,CFG_STM32_GPIO,y) 166endif 167 168# if any crypto driver is enabled, enable the crypto-framework layer 169ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 170$(call force,CFG_STM32_CRYPTO_DRIVER,y) 171endif 172 173CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 174$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 175 176CFG_WDT ?= $(CFG_STM32_IWDG) 177 178# Platform specific configuration 179CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 180 181# SiP/OEM service for non-secure world 182CFG_STM32_BSEC_SIP ?= n 183CFG_STM32MP1_SCMI_SIP ?= n 184ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 185$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 186$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 187$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 188endif 189 190# Enable BSEC PTA for fuses access management 191CFG_STM32_BSEC_PTA ?= y 192ifeq ($(CFG_STM32_BSEC_PTA),y) 193$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 194endif 195 196# Default enable SCMI PTA support 197CFG_SCMI_PTA ?= y 198ifeq ($(CFG_SCMI_PTA),y) 199$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 200$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 201CFG_SCMI_MSG_SHM_MSG ?= y 202CFG_SCMI_MSG_SMT ?= y 203endif 204 205CFG_SCMI_MSG_DRIVERS ?= n 206ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 207$(call force,CFG_SCMI_MSG_CLOCK,y) 208$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 209CFG_SCMI_MSG_SHM_MSG ?= y 210CFG_SCMI_MSG_SMT ?= y 211CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 212$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 213endif 214 215ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 216CFG_HWRNG_PTA ?= y 217endif 218ifeq ($(CFG_HWRNG_PTA),y) 219$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 220$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 221$(call force,CFG_HWRNG_QUALITY,1024) 222endif 223 224# Provision enough threads to pass xtest 225ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 226ifeq ($(CFG_WITH_PAGER),y) 227CFG_NUM_THREADS ?= 3 228else 229CFG_NUM_THREADS ?= 10 230endif 231endif 232 233# Default enable some test facitilites 234CFG_ENABLE_EMBEDDED_TESTS ?= y 235CFG_WITH_STATS ?= y 236 237# Enable OTP update with BSEC driver 238CFG_STM32_BSEC_WRITE ?= y 239 240# Default disable some support for pager memory size constraint 241ifeq ($(CFG_WITH_PAGER),y) 242CFG_TEE_CORE_DEBUG ?= n 243CFG_UNWIND ?= n 244CFG_LOCKDEP ?= n 245CFG_TA_BGET_TEST ?= n 246# Default disable early TA compression to support a smaller HEAP size 247CFG_EARLY_TA_COMPRESS ?= n 248CFG_CORE_HEAP_SIZE ?= 49152 249endif 250 251# Non-secure UART and GPIO/pinctrl for the output console 252CFG_WITH_NSEC_GPIOS ?= y 253CFG_WITH_NSEC_UARTS ?= y 254# UART instance used for early console (0 disables early console) 255CFG_STM32_EARLY_CONSOLE_UART ?= 4 256 257# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 258# Disable the HUK by default as it requires a product specific configuration. 259# 260# Configuration must provide OTP indices where HUK is loaded. 261# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 262# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 263# 264# Configuration must provide the HUK generation scheme. The following switches 265# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 266# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 267# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 268# content derived with the device UID fuses content. See derivation scheme 269# in stm32mp15_huk.c implementation. 270CFG_STM32MP15_HUK ?= n 271 272ifeq ($(CFG_STM32MP15_HUK),y) 273ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 274$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 275$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 276$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 277$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 278endif 279ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 280$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 281endif 282ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 283$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 284endif 285ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 286$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 287endif 288ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 289$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 290endif 291 292CFG_STM32MP15_HUK_BSEC_KEY ?= y 293CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 294ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 295$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 296else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 297$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 298endif 299endif # CFG_STM32MP15_HUK 300 301# Sanity on choice config switches 302ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 303$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 304endif 305