1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8flavor_dts_file-157A_DK1_SCMI = stm32mp157a-dk1-scmi.dts 9flavor_dts_file-157C_DK2_SCMI = stm32mp157c-dk2-scmi.dts 10flavor_dts_file-157C_ED1_SCMI = stm32mp157c-ed1-scmi.dts 11flavor_dts_file-157C_EV1_SCMI = stm32mp157c-ev1-scmi.dts 12 13flavor_dts_file-135F_DK = stm32mp135f-dk.dts 14 15flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 16 $(flavor_dts_file-157C_DK2_SCMI) \ 17 $(flavor_dts_file-135F_DK) 18 19flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) \ 20 $(flavor_dts_file-157A_DK1_SCMI) 21 22flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 23 $(flavor_dts_file-157C_ED1) \ 24 $(flavor_dts_file-157C_EV1) \ 25 $(flavor_dts_file-157C_ED1_SCMI) \ 26 $(flavor_dts_file-157C_EV1_SCMI) 27 28flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 29 30flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 31 $(flavorlist-no_cryp-1G) 32 33flavorlist-512M = $(flavorlist-cryp-512M) \ 34 $(flavorlist-no_cryp-512M) 35 36flavorlist-1G = $(flavorlist-cryp-1G) \ 37 $(flavorlist-no_cryp-1G) 38 39flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 40 $(flavor_dts_file-157C_DK2) \ 41 $(flavor_dts_file-157C_ED1) \ 42 $(flavor_dts_file-157C_EV1) \ 43 $(flavor_dts_file-157A_DK1_SCMI) \ 44 $(flavor_dts_file-157C_DK2_SCMI) \ 45 $(flavor_dts_file-157C_ED1_SCMI) \ 46 $(flavor_dts_file-157C_EV1_SCMI) 47 48flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 49 $(flavor_dts_file-157A_DK1) \ 50 $(flavor_dts_file-157C_DHCOM_PDK2) \ 51 $(flavor_dts_file-157C_DK2) \ 52 $(flavor_dts_file-157C_ED1) \ 53 $(flavor_dts_file-157C_EV1) \ 54 $(flavor_dts_file-157A_DK1_SCMI) \ 55 $(flavor_dts_file-157C_DK2_SCMI) \ 56 $(flavor_dts_file-157C_ED1_SCMI) \ 57 $(flavor_dts_file-157C_EV1_SCMI) 58 59flavorlist-MP13 = $(flavor_dts_file-135F_DK) 60 61ifneq ($(PLATFORM_FLAVOR),) 62ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 63$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 64endif 65CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 66endif 67CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 68 69ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 70$(call force,CFG_STM32_CRYP,n) 71$(call force,CFG_STM32_SAES,n) 72endif 73 74ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 75$(call force,CFG_HWRNG_PTA,n) 76$(call force,CFG_WITH_SOFTWARE_PRNG,y) 77endif 78 79ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 80CFG_STM32MP15_HUK ?= y 81CFG_STM32_HUK_FROM_DT ?= y 82endif 83 84ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 85$(call force,CFG_STM32MP13,y) 86endif 87 88ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 89$(call force,CFG_STM32MP15,y) 90endif 91 92# CFG_STM32MP1x switches are exclusive. 93# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 94# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 95ifeq ($(CFG_STM32MP13),y) 96$(call force,CFG_STM32MP15,n) 97else 98$(call force,CFG_STM32MP15,y) 99$(call force,CFG_STM32MP13,n) 100endif 101ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 102$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 103endif 104ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 105$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 106endif 107 108include core/arch/arm/cpu/cortex-a7.mk 109 110$(call force,CFG_DRIVERS_CLK,y) 111$(call force,CFG_DRIVERS_CLK_DT,y) 112$(call force,CFG_DRIVERS_GPIO,y) 113$(call force,CFG_DRIVERS_PINCTRL,y) 114$(call force,CFG_DRIVERS_REGULATOR,y) 115$(call force,CFG_GIC,y) 116$(call force,CFG_INIT_CNTVOFF,y) 117$(call force,CFG_PSCI_ARM32,y) 118$(call force,CFG_REGULATOR_FIXED,y) 119$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 120$(call force,CFG_SM_PLATFORM_HANDLER,y) 121$(call force,CFG_STM32_SHARED_IO,y) 122 123ifeq ($(CFG_STM32MP13),y) 124$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 125$(call force,CFG_CORE_ASYNC_NOTIF,y) 126$(call force,CFG_CORE_ASYNC_NOTIF_GIC_INTID,31) 127$(call force,CFG_CORE_RESERVED_SHM,n) 128$(call force,CFG_DRIVERS_CLK_FIXED,y) 129$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 130$(call force,CFG_STM32_GPIO,y) 131$(call force,CFG_STM32_VREFBUF,y) 132$(call force,CFG_STM32MP_CLK_CORE,y) 133$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 134$(call force,CFG_STM32MP1_RSTCTRL,y) 135$(call force,CFG_STM32MP13_CLK,y) 136$(call force,CFG_STM32MP13_REGULATOR_IOD,y) 137$(call force,CFG_TEE_CORE_NB_CORE,1) 138$(call force,CFG_WITH_NSEC_GPIOS,n) 139CFG_EXTERNAL_DT ?= n 140CFG_STM32MP_OPP_COUNT ?= 2 141CFG_WITH_PAGER ?= n 142endif # CFG_STM32MP13 143 144ifeq ($(CFG_STM32MP15),y) 145$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 146$(call force,CFG_DRIVERS_CLK_FIXED,n) 147$(call force,CFG_HALT_CORES_ON_PANIC_SGI,15) 148$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 149$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 150$(call force,CFG_STM32_SAES,n) 151$(call force,CFG_STM32MP1_RSTCTRL,y) 152$(call force,CFG_STM32MP15_CLK,y) 153CFG_CORE_RESERVED_SHM ?= n 154CFG_HALT_CORES_ON_PANIC ?= y 155CFG_EXTERNAL_DT ?= y 156CFG_STM32_BSEC_SIP ?= y 157CFG_TEE_CORE_NB_CORE ?= 2 158CFG_WITH_PAGER ?= y 159CFG_WITH_SOFTWARE_PRNG ?= y 160endif # CFG_STM32MP15 161 162ifeq ($(CFG_WITH_PAGER),y) 163CFG_WITH_LPAE ?= n 164endif 165CFG_WITH_LPAE ?= y 166CFG_MMAP_REGIONS ?= 23 167CFG_DTB_MAX_SIZE ?= (256 * 1024) 168CFG_CORE_ASLR ?= n 169 170CFG_STM32MP_REMOTEPROC ?= n 171CFG_DRIVERS_REMOTEPROC ?= $(CFG_STM32MP_REMOTEPROC) 172CFG_REMOTEPROC_PTA ?= $(CFG_STM32MP_REMOTEPROC) 173ifeq ($(CFG_REMOTEPROC_PTA),y) 174# Remoteproc early TA for coprocessor firmware management in boot stages 175CFG_IN_TREE_EARLY_TAS += remoteproc/80a4c275-0a47-4905-8285-1486a9771a08 176# Embed public part of this key in OP-TEE OS 177RPROC_SIGN_KEY ?= keys/default.pem 178endif 179 180ifneq ($(CFG_WITH_LPAE),y) 181# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 182CFG_TEE_RAM_VA_SIZE ?= 0x00200000 183endif 184 185ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 186CFG_TZDRAM_START ?= 0xde000000 187CFG_DRAM_SIZE ?= 0x20000000 188endif 189 190CFG_DRAM_BASE ?= 0xc0000000 191CFG_DRAM_SIZE ?= 0x40000000 192 193# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 194# device memory mapped SRAM used for SCMI message transfers. 195# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 196# native shared memory for SCMI communication instead of SRAM. 197# 198# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 199# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 200# disabled. 201CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 202ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 203$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 204else 205CFG_STM32MP1_SCMI_SHM_BASE ?= 0 206endif 207$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 208 209ifeq ($(CFG_STM32MP15),y) 210CFG_TZDRAM_START ?= 0xfe000000 211ifeq ($(CFG_CORE_RESERVED_SHM),y) 212CFG_TZDRAM_SIZE ?= 0x01e00000 213else 214CFG_TZDRAM_SIZE ?= 0x02000000 215endif 216CFG_TZSRAM_START ?= 0x2ffc0000 217CFG_TZSRAM_SIZE ?= 0x0003f000 218ifeq ($(CFG_CORE_RESERVED_SHM),y) 219CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 220CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 221endif 222else 223CFG_TZDRAM_SIZE ?= 0x02000000 224CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 225endif #CFG_STM32MP15 226 227CFG_STM32_BSEC ?= y 228CFG_STM32_CRYP ?= y 229CFG_STM32_ETZPC ?= y 230CFG_STM32_GPIO ?= y 231CFG_STM32_I2C ?= y 232CFG_STM32_IWDG ?= y 233CFG_STM32_RNG ?= y 234CFG_STM32_RSTCTRL ?= y 235CFG_STM32_SAES ?= y 236CFG_STM32_TAMP ?= y 237CFG_STM32_UART ?= y 238CFG_STPMIC1 ?= y 239CFG_TZC400 ?= y 240 241CFG_DRIVERS_I2C ?= $(CFG_STM32_I2C) 242CFG_REGULATOR_GPIO ?= $(CFG_STM32_GPIO) 243 244CFG_WITH_SOFTWARE_PRNG ?= n 245ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 246$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 247endif 248 249ifeq ($(CFG_STPMIC1),y) 250$(call force,CFG_STM32_I2C,y) 251$(call force,CFG_STM32_GPIO,y) 252endif 253 254# If any crypto driver is enabled, enable the crypto-framework layer 255ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y) 256$(call force,CFG_STM32_CRYPTO_DRIVER,y) 257endif 258 259CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 260$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 261 262CFG_WDT ?= $(CFG_STM32_IWDG) 263CFG_WDT_SM_HANDLER ?= $(CFG_WDT) 264CFG_WDT_SM_HANDLER_ID ?= 0xbc000000 265 266# Platform specific configuration 267CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 268 269# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 270ifneq ($(CFG_SCMI_SCPFW),y) 271CFG_SCMI_MSG_DRIVERS ?= y 272endif 273 274# SiP/OEM service for non-secure world 275CFG_STM32_BSEC_SIP ?= n 276CFG_STM32MP1_SCMI_SIP ?= n 277ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 278$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 279$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 280$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 281endif 282 283# Enable BSEC PTA for fuses access management 284CFG_STM32_BSEC_PTA ?= y 285ifeq ($(CFG_STM32_BSEC_PTA),y) 286$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 287endif 288 289# Default enable SCMI PTA support 290CFG_SCMI_PTA ?= y 291ifeq ($(CFG_SCMI_PTA),y) 292ifneq ($(CFG_SCMI_SCPFW),y) 293$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 294CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 295CFG_SCMI_MSG_SHM_MSG ?= y 296CFG_SCMI_MSG_SMT ?= y 297endif # !CFG_SCMI_SCPFW 298endif # CFG_SCMI_PTA 299 300CFG_SCMI_SCPFW ?= n 301ifeq ($(CFG_SCMI_SCPFW),y) 302$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1) 303endif 304 305CFG_SCMI_MSG_DRIVERS ?= n 306ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 307$(call force,CFG_SCMI_MSG_CLOCK,y) 308$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 309CFG_SCMI_MSG_SHM_MSG ?= y 310CFG_SCMI_MSG_SMT ?= y 311CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 312$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 313endif 314 315ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 316CFG_HWRNG_PTA ?= y 317endif 318ifeq ($(CFG_HWRNG_PTA),y) 319$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 320$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 321$(call force,CFG_HWRNG_QUALITY,1024) 322endif 323 324# Provision enough threads to pass xtest 325ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 326ifeq ($(CFG_WITH_PAGER),y) 327CFG_NUM_THREADS ?= 3 328else 329CFG_NUM_THREADS ?= 10 330endif 331endif 332 333# Default enable some test facitilites 334CFG_ENABLE_EMBEDDED_TESTS ?= y 335CFG_WITH_STATS ?= y 336 337# Default enable software fallback on crypto drivers 338CFG_STM32_SAES_SW_FALLBACK ?= y 339 340# Enable OTP update with BSEC driver 341CFG_STM32_BSEC_WRITE ?= y 342 343# Default disable some support for pager memory size constraint 344ifeq ($(CFG_WITH_PAGER),y) 345CFG_TEE_CORE_DEBUG ?= n 346CFG_UNWIND ?= n 347CFG_LOCKDEP ?= n 348CFG_TA_BGET_TEST ?= n 349# Default disable early TA compression to support a smaller HEAP size 350CFG_EARLY_TA_COMPRESS ?= n 351CFG_CORE_HEAP_SIZE ?= 49152 352endif 353 354# Non-secure UART and GPIO/pinctrl for the output console 355CFG_WITH_NSEC_GPIOS ?= y 356CFG_WITH_NSEC_UARTS ?= y 357# UART instance used for early console (0 disables early console) 358CFG_STM32_EARLY_CONSOLE_UART ?= 4 359 360# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 361# Disable the HUK by default as it requires a product specific configuration. 362# 363# Configuration must provide OTP indices where HUK is loaded. 364# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 365# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 366# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 367# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 368# 369# Configuration must provide the HUK generation scheme. The following switches 370# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 371# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 372# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 373# content derived with the device UID fuses content. See derivation scheme 374# in stm32mp15_huk.c implementation. 375CFG_STM32MP15_HUK ?= n 376CFG_STM32_HUK_FROM_DT ?= n 377 378ifeq ($(CFG_STM32MP15_HUK),y) 379ifneq ($(CFG_STM32_HUK_FROM_DT),y) 380ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 381$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 382$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 383$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 384$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 385endif 386ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 387$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 388endif 389ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 390$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 391endif 392ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 393$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 394endif 395ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 396$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 397endif 398endif # CFG_STM32_HUK_FROM_DT 399 400CFG_STM32MP15_HUK_BSEC_KEY ?= y 401CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 402ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 403$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 404else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 405$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 406endif 407endif # CFG_STM32MP15_HUK 408 409CFG_TEE_CORE_DEBUG ?= y 410CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 411 412# Sanity on choice config switches 413ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 414$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 415endif 416