1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 32 $(flavor_dts_file-157A_DK1) \ 33 $(flavor_dts_file-157C_DHCOM_PDK2) \ 34 $(flavor_dts_file-157C_DK2) \ 35 $(flavor_dts_file-157C_ED1) \ 36 $(flavor_dts_file-157C_EV1) 37 38flavorlist-MP13 = $(flavor_dts_file-135F_DK) 39 40ifneq ($(PLATFORM_FLAVOR),) 41ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 42$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 43endif 44CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 45endif 46 47ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 48$(call force,CFG_STM32_CRYP,n) 49endif 50 51ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 52$(call force,CFG_STM32MP13,y) 53endif 54 55ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 56$(call force,CFG_STM32MP15,y) 57endif 58 59# CFG_STM32MP1x switches are exclusive. 60# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 61# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 62ifeq ($(CFG_STM32MP13),y) 63$(call force,CFG_STM32MP15,n) 64else 65$(call force,CFG_STM32MP15,y) 66$(call force,CFG_STM32MP13,n) 67endif 68ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 69$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 70endif 71ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 72$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 73endif 74 75include core/arch/arm/cpu/cortex-a7.mk 76 77$(call force,CFG_DRIVERS_CLK,y) 78$(call force,CFG_GIC,y) 79$(call force,CFG_INIT_CNTVOFF,y) 80$(call force,CFG_PSCI_ARM32,y) 81$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 82$(call force,CFG_SM_PLATFORM_HANDLER,y) 83$(call force,CFG_STM32_SHARED_IO,y) 84 85ifeq ($(CFG_STM32MP13),y) 86$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 87$(call force,CFG_CORE_RESERVED_SHM,n) 88$(call force,CFG_DRIVERS_CLK_FIXED,y) 89$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 90$(call force,CFG_STM32_GPIO,y) 91$(call force,CFG_STM32_RNG,n) 92$(call force,CFG_STM32MP_CLK_CORE,y) 93$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 94$(call force,CFG_STM32MP13_CLK,y) 95$(call force,CFG_TEE_CORE_NB_CORE,1) 96$(call force,CFG_WITH_NSEC_GPIOS,n) 97CFG_EXTERNAL_DT ?= n 98CFG_STM32MP_OPP_COUNT ?= 2 99CFG_WITH_PAGER ?= n 100endif # CFG_STM32MP13 101 102ifeq ($(CFG_STM32MP15),y) 103$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 104$(call force,CFG_DRIVERS_CLK_FIXED,n) 105$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 106$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 107$(call force,CFG_STM32MP15_CLK,y) 108CFG_CORE_RESERVED_SHM ?= y 109CFG_EXTERNAL_DT ?= y 110CFG_STM32_BSEC_SIP ?= y 111CFG_TEE_CORE_NB_CORE ?= 2 112CFG_WITH_PAGER ?= y 113endif # CFG_STM32MP15 114 115CFG_WITH_LPAE ?= y 116CFG_WITH_SOFTWARE_PRNG ?= y 117CFG_MMAP_REGIONS ?= 23 118CFG_DTB_MAX_SIZE ?= (256 * 1024) 119CFG_CORE_ASLR ?= n 120 121ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),) 122# Some drivers mandate DT support 123$(call force,CFG_DRIVERS_CLK_DT,n) 124$(call force,CFG_STM32_CRYP,n) 125$(call force,CFG_STM32_GPIO,n) 126$(call force,CFG_STM32_I2C,n) 127$(call force,CFG_STM32_IWDG,n) 128$(call force,CFG_STM32_TAMP,n) 129$(call force,CFG_STPMIC1,n) 130$(call force,CFG_STM32MP1_SCMI_SIP,n) 131$(call force,CFG_SCMI_PTA,n) 132else 133$(call force,CFG_DRIVERS_CLK_DT,y) 134endif 135 136ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 137CFG_TZDRAM_START ?= 0xde000000 138CFG_DRAM_SIZE ?= 0x20000000 139endif 140 141CFG_DRAM_BASE ?= 0xc0000000 142CFG_DRAM_SIZE ?= 0x40000000 143CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 144CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 145ifeq ($(CFG_STM32MP15),y) 146CFG_TZDRAM_START ?= 0xfe000000 147ifeq ($(CFG_CORE_RESERVED_SHM),y) 148CFG_TZDRAM_SIZE ?= 0x01e00000 149else 150CFG_TZDRAM_SIZE ?= 0x02000000 151endif 152CFG_TZSRAM_START ?= 0x2ffc0000 153CFG_TZSRAM_SIZE ?= 0x0003f000 154ifeq ($(CFG_CORE_RESERVED_SHM),y) 155CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 156CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 157endif 158else 159CFG_TZDRAM_SIZE ?= 0x02000000 160CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 161endif #CFG_STM32MP15 162 163CFG_STM32_BSEC ?= y 164CFG_STM32_CRYP ?= y 165CFG_STM32_ETZPC ?= y 166CFG_STM32_GPIO ?= y 167CFG_STM32_I2C ?= y 168CFG_STM32_IWDG ?= y 169CFG_STM32_RNG ?= y 170CFG_STM32_RSTCTRL ?= y 171CFG_STM32_TAMP ?= y 172CFG_STM32_UART ?= y 173CFG_STPMIC1 ?= y 174CFG_TZC400 ?= y 175 176ifeq ($(CFG_STPMIC1),y) 177$(call force,CFG_STM32_I2C,y) 178$(call force,CFG_STM32_GPIO,y) 179endif 180 181# if any crypto driver is enabled, enable the crypto-framework layer 182ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 183$(call force,CFG_STM32_CRYPTO_DRIVER,y) 184endif 185 186CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 187$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 188 189CFG_WDT ?= $(CFG_STM32_IWDG) 190 191# Platform specific configuration 192CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 193 194# SiP/OEM service for non-secure world 195CFG_STM32_BSEC_SIP ?= n 196CFG_STM32MP1_SCMI_SIP ?= n 197ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 198$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 199$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 200$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 201endif 202 203# Enable BSEC PTA for fuses access management 204CFG_STM32_BSEC_PTA ?= y 205ifeq ($(CFG_STM32_BSEC_PTA),y) 206$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 207endif 208 209# Default enable SCMI PTA support 210CFG_SCMI_PTA ?= y 211ifeq ($(CFG_SCMI_PTA),y) 212$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 213$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 214CFG_SCMI_MSG_SHM_MSG ?= y 215CFG_SCMI_MSG_SMT ?= y 216endif 217 218CFG_SCMI_MSG_DRIVERS ?= n 219ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 220$(call force,CFG_SCMI_MSG_CLOCK,y) 221$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 222CFG_SCMI_MSG_SHM_MSG ?= y 223CFG_SCMI_MSG_SMT ?= y 224CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 225$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 226endif 227 228ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 229CFG_HWRNG_PTA ?= y 230endif 231ifeq ($(CFG_HWRNG_PTA),y) 232$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 233$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 234$(call force,CFG_HWRNG_QUALITY,1024) 235endif 236 237# Provision enough threads to pass xtest 238ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 239ifeq ($(CFG_WITH_PAGER),y) 240CFG_NUM_THREADS ?= 3 241else 242CFG_NUM_THREADS ?= 10 243endif 244endif 245 246# Default enable some test facitilites 247CFG_ENABLE_EMBEDDED_TESTS ?= y 248CFG_WITH_STATS ?= y 249 250# Enable OTP update with BSEC driver 251CFG_STM32_BSEC_WRITE ?= y 252 253# Default disable some support for pager memory size constraint 254ifeq ($(CFG_WITH_PAGER),y) 255CFG_TEE_CORE_DEBUG ?= n 256CFG_UNWIND ?= n 257CFG_LOCKDEP ?= n 258CFG_TA_BGET_TEST ?= n 259# Default disable early TA compression to support a smaller HEAP size 260CFG_EARLY_TA_COMPRESS ?= n 261CFG_CORE_HEAP_SIZE ?= 49152 262endif 263 264# Non-secure UART and GPIO/pinctrl for the output console 265CFG_WITH_NSEC_GPIOS ?= y 266CFG_WITH_NSEC_UARTS ?= y 267# UART instance used for early console (0 disables early console) 268CFG_STM32_EARLY_CONSOLE_UART ?= 4 269 270# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 271# Disable the HUK by default as it requires a product specific configuration. 272# 273# Configuration must provide OTP indices where HUK is loaded. 274# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 275# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 276# 277# Configuration must provide the HUK generation scheme. The following switches 278# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 279# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 280# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 281# content derived with the device UID fuses content. See derivation scheme 282# in stm32mp15_huk.c implementation. 283CFG_STM32MP15_HUK ?= n 284 285ifeq ($(CFG_STM32MP15_HUK),y) 286ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 287$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 288$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 289$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 290$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 291endif 292ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 293$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 294endif 295ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 296$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 297endif 298ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 299$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 300endif 301ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 302$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 303endif 304 305CFG_STM32MP15_HUK_BSEC_KEY ?= y 306CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 307ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 308$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 309else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 310$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 311endif 312endif # CFG_STM32MP15_HUK 313 314# Sanity on choice config switches 315ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 316$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 317endif 318