1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 32 $(flavor_dts_file-157A_DK1) \ 33 $(flavor_dts_file-157C_DHCOM_PDK2) \ 34 $(flavor_dts_file-157C_DK2) \ 35 $(flavor_dts_file-157C_ED1) \ 36 $(flavor_dts_file-157C_EV1) 37 38flavorlist-MP13 = $(flavor_dts_file-135F_DK) 39 40ifneq ($(PLATFORM_FLAVOR),) 41ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 42$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 43endif 44CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 45endif 46 47ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 48$(call force,CFG_STM32_CRYP,n) 49endif 50 51ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 52$(call force,CFG_STM32MP13,y) 53endif 54 55ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 56$(call force,CFG_STM32MP15,y) 57endif 58 59# CFG_STM32MP1x switches are exclusive. 60# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 61# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 62ifeq ($(CFG_STM32MP13),y) 63$(call force,CFG_STM32MP15,n) 64else 65$(call force,CFG_STM32MP15,y) 66$(call force,CFG_STM32MP13,n) 67endif 68ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 69$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 70endif 71ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 72$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 73endif 74 75include core/arch/arm/cpu/cortex-a7.mk 76 77$(call force,CFG_DRIVERS_CLK,y) 78$(call force,CFG_GIC,y) 79$(call force,CFG_INIT_CNTVOFF,y) 80$(call force,CFG_PSCI_ARM32,y) 81$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 82$(call force,CFG_SM_PLATFORM_HANDLER,y) 83$(call force,CFG_STM32_SHARED_IO,y) 84 85ifeq ($(CFG_STM32MP13),y) 86$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 87$(call force,CFG_CORE_RESERVED_SHM,n) 88$(call force,CFG_DRIVERS_CLK_FIXED,y) 89$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 90$(call force,CFG_STM32_GPIO,y) 91$(call force,CFG_STM32_RNG,n) 92$(call force,CFG_STM32MP_CLK_CORE,y) 93$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 94$(call force,CFG_STM32MP13_CLK,y) 95$(call force,CFG_TEE_CORE_NB_CORE,1) 96$(call force,CFG_WITH_NSEC_GPIOS,n) 97CFG_STM32MP_OPP_COUNT ?= 2 98CFG_WITH_PAGER ?= n 99endif # CFG_STM32MP13 100 101ifeq ($(CFG_STM32MP15),y) 102$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 103$(call force,CFG_DRIVERS_CLK_FIXED,n) 104$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 105$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 106$(call force,CFG_STM32MP15_CLK,y) 107CFG_CORE_RESERVED_SHM ?= y 108CFG_TEE_CORE_NB_CORE ?= 2 109CFG_WITH_PAGER ?= y 110endif # CFG_STM32MP15 111 112CFG_WITH_LPAE ?= y 113CFG_WITH_SOFTWARE_PRNG ?= y 114CFG_MMAP_REGIONS ?= 23 115CFG_DTB_MAX_SIZE ?= (256 * 1024) 116CFG_CORE_ASLR ?= n 117 118ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),) 119# Some drivers mandate DT support 120$(call force,CFG_DRIVERS_CLK_DT,n) 121$(call force,CFG_STM32_CRYP,n) 122$(call force,CFG_STM32_GPIO,n) 123$(call force,CFG_STM32_I2C,n) 124$(call force,CFG_STM32_IWDG,n) 125$(call force,CFG_STM32_TAMP,n) 126$(call force,CFG_STPMIC1,n) 127$(call force,CFG_STM32MP1_SCMI_SIP,n) 128$(call force,CFG_SCMI_PTA,n) 129else 130$(call force,CFG_DRIVERS_CLK_DT,y) 131endif 132 133ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 134CFG_TZDRAM_START ?= 0xde000000 135CFG_DRAM_SIZE ?= 0x20000000 136endif 137 138CFG_DRAM_BASE ?= 0xc0000000 139CFG_DRAM_SIZE ?= 0x40000000 140CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 141CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 142ifeq ($(CFG_STM32MP15),y) 143CFG_TZDRAM_START ?= 0xfe000000 144CFG_TZDRAM_SIZE ?= 0x01e00000 145CFG_TZSRAM_START ?= 0x2ffc0000 146CFG_TZSRAM_SIZE ?= 0x0003f000 147ifeq ($(CFG_CORE_RESERVED_SHM),y) 148CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 149CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 150endif 151else 152CFG_TZDRAM_SIZE ?= 0x02000000 153CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 154endif #CFG_STM32MP15 155 156CFG_STM32_BSEC ?= y 157CFG_STM32_CRYP ?= y 158CFG_STM32_ETZPC ?= y 159CFG_STM32_GPIO ?= y 160CFG_STM32_I2C ?= y 161CFG_STM32_IWDG ?= y 162CFG_STM32_RNG ?= y 163CFG_STM32_RSTCTRL ?= y 164CFG_STM32_TAMP ?= y 165CFG_STM32_UART ?= y 166CFG_STPMIC1 ?= y 167CFG_TZC400 ?= y 168 169ifeq ($(CFG_STPMIC1),y) 170$(call force,CFG_STM32_I2C,y) 171$(call force,CFG_STM32_GPIO,y) 172endif 173 174# if any crypto driver is enabled, enable the crypto-framework layer 175ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 176$(call force,CFG_STM32_CRYPTO_DRIVER,y) 177endif 178 179CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 180$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 181 182CFG_WDT ?= $(CFG_STM32_IWDG) 183 184# Platform specific configuration 185CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 186 187# SiP/OEM service for non-secure world 188CFG_STM32_BSEC_SIP ?= y 189CFG_STM32MP1_SCMI_SIP ?= n 190ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 191$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 192$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 193$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 194endif 195 196# Default enable SCMI PTA support 197CFG_SCMI_PTA ?= y 198ifeq ($(CFG_SCMI_PTA),y) 199$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 200$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 201CFG_SCMI_MSG_SHM_MSG ?= y 202CFG_SCMI_MSG_SMT ?= y 203endif 204 205CFG_SCMI_MSG_DRIVERS ?= n 206ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 207$(call force,CFG_SCMI_MSG_CLOCK,y) 208$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 209CFG_SCMI_MSG_SHM_MSG ?= y 210CFG_SCMI_MSG_SMT ?= y 211CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 212$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 213endif 214 215ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 216CFG_HWRNG_PTA ?= y 217endif 218ifeq ($(CFG_HWRNG_PTA),y) 219$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 220$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 221$(call force,CFG_HWRNG_QUALITY,1024) 222endif 223 224# Provision enough threads to pass xtest 225ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 226ifeq ($(CFG_WITH_PAGER),y) 227CFG_NUM_THREADS ?= 3 228else 229CFG_NUM_THREADS ?= 10 230endif 231endif 232 233# Default enable some test facitilites 234CFG_ENABLE_EMBEDDED_TESTS ?= y 235CFG_WITH_STATS ?= y 236 237# Enable to allow debug 238CFG_STM32_BSEC_WRITE ?= $(CFG_TEE_CORE_DEBUG) 239 240# Default disable some support for pager memory size constraint 241ifeq ($(CFG_WITH_PAGER),y) 242CFG_TEE_CORE_DEBUG ?= n 243CFG_UNWIND ?= n 244CFG_LOCKDEP ?= n 245CFG_TA_BGET_TEST ?= n 246# Default disable early TA compression to support a smaller HEAP size 247CFG_EARLY_TA_COMPRESS ?= n 248CFG_CORE_HEAP_SIZE ?= 49152 249endif 250 251# Non-secure UART and GPIO/pinctrl for the output console 252CFG_WITH_NSEC_GPIOS ?= y 253CFG_WITH_NSEC_UARTS ?= y 254# UART instance used for early console (0 disables early console) 255CFG_STM32_EARLY_CONSOLE_UART ?= 4 256 257# Sanity on choice config switches 258ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 259$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 260endif 261