1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 32 $(flavor_dts_file-157C_DK2) \ 33 $(flavor_dts_file-157C_ED1) \ 34 $(flavor_dts_file-157C_EV1) 35 36flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 37 $(flavor_dts_file-157A_DK1) \ 38 $(flavor_dts_file-157C_DHCOM_PDK2) \ 39 $(flavor_dts_file-157C_DK2) \ 40 $(flavor_dts_file-157C_ED1) \ 41 $(flavor_dts_file-157C_EV1) 42 43flavorlist-MP13 = $(flavor_dts_file-135F_DK) 44 45ifneq ($(PLATFORM_FLAVOR),) 46ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 47$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 48endif 49CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 50endif 51CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 52 53ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 54$(call force,CFG_STM32_CRYP,n) 55$(call force,CFG_STM32_SAES,n) 56endif 57 58ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 59$(call force,CFG_HWRNG_PTA,n) 60$(call force,CFG_WITH_SOFTWARE_PRNG,y) 61endif 62 63ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 64CFG_STM32MP15_HUK ?= y 65CFG_STM32_HUK_FROM_DT ?= y 66endif 67 68ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 69$(call force,CFG_STM32MP13,y) 70endif 71 72ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 73$(call force,CFG_STM32MP15,y) 74endif 75 76# CFG_STM32MP1x switches are exclusive. 77# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 78# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 79ifeq ($(CFG_STM32MP13),y) 80$(call force,CFG_STM32MP15,n) 81else 82$(call force,CFG_STM32MP15,y) 83$(call force,CFG_STM32MP13,n) 84endif 85ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 86$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 87endif 88ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 89$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 90endif 91 92include core/arch/arm/cpu/cortex-a7.mk 93 94$(call force,CFG_DRIVERS_CLK,y) 95$(call force,CFG_DRIVERS_CLK_DT,y) 96$(call force,CFG_DRIVERS_GPIO,y) 97$(call force,CFG_DRIVERS_PINCTRL,y) 98$(call force,CFG_DRIVERS_REGULATOR,y) 99$(call force,CFG_GIC,y) 100$(call force,CFG_INIT_CNTVOFF,y) 101$(call force,CFG_PSCI_ARM32,y) 102$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 103$(call force,CFG_SM_PLATFORM_HANDLER,y) 104$(call force,CFG_STM32_SHARED_IO,y) 105 106ifeq ($(CFG_STM32MP13),y) 107$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 108$(call force,CFG_CORE_RESERVED_SHM,n) 109$(call force,CFG_DRIVERS_CLK_FIXED,y) 110$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 111$(call force,CFG_STM32_GPIO,y) 112$(call force,CFG_STM32MP_CLK_CORE,y) 113$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 114$(call force,CFG_STM32MP13_CLK,y) 115$(call force,CFG_TEE_CORE_NB_CORE,1) 116$(call force,CFG_WITH_NSEC_GPIOS,n) 117CFG_EXTERNAL_DT ?= n 118CFG_STM32MP_OPP_COUNT ?= 2 119CFG_STM32MP1_SCMI_SHM_SYSRAM ?= y 120CFG_WITH_PAGER ?= n 121endif # CFG_STM32MP13 122 123ifeq ($(CFG_STM32MP15),y) 124$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 125$(call force,CFG_DRIVERS_CLK_FIXED,n) 126$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 127$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 128$(call force,CFG_STM32_SAES,n) 129$(call force,CFG_STM32MP15_CLK,y) 130CFG_CORE_RESERVED_SHM ?= y 131CFG_EXTERNAL_DT ?= y 132CFG_STM32_BSEC_SIP ?= y 133CFG_TEE_CORE_NB_CORE ?= 2 134CFG_WITH_PAGER ?= y 135CFG_WITH_SOFTWARE_PRNG ?= y 136endif # CFG_STM32MP15 137 138ifeq ($(CFG_WITH_PAGER),y) 139CFG_WITH_LPAE ?= n 140endif 141CFG_WITH_LPAE ?= y 142CFG_MMAP_REGIONS ?= 23 143CFG_DTB_MAX_SIZE ?= (256 * 1024) 144CFG_CORE_ASLR ?= n 145 146ifneq ($(CFG_WITH_LPAE),y) 147# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 148CFG_TEE_RAM_VA_SIZE ?= 0x00200000 149endif 150 151ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 152CFG_TZDRAM_START ?= 0xde000000 153CFG_DRAM_SIZE ?= 0x20000000 154endif 155 156CFG_DRAM_BASE ?= 0xc0000000 157CFG_DRAM_SIZE ?= 0x40000000 158 159# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 160# device memory mapped SRAM used for SCMI message transfers. 161# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 162# native shared memory for SCMI communication instead of SRAM. 163# 164# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 165# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 166# disabled. 167CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 168ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 169$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 170else 171CFG_STM32MP1_SCMI_SHM_BASE ?= 0 172endif 173$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 174 175ifeq ($(CFG_STM32MP15),y) 176CFG_TZDRAM_START ?= 0xfe000000 177ifeq ($(CFG_CORE_RESERVED_SHM),y) 178CFG_TZDRAM_SIZE ?= 0x01e00000 179else 180CFG_TZDRAM_SIZE ?= 0x02000000 181endif 182CFG_TZSRAM_START ?= 0x2ffc0000 183CFG_TZSRAM_SIZE ?= 0x0003f000 184ifeq ($(CFG_CORE_RESERVED_SHM),y) 185CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 186CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 187endif 188else 189CFG_TZDRAM_SIZE ?= 0x02000000 190CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 191endif #CFG_STM32MP15 192 193CFG_STM32_BSEC ?= y 194CFG_STM32_CRYP ?= y 195CFG_STM32_ETZPC ?= y 196CFG_STM32_GPIO ?= y 197CFG_STM32_I2C ?= y 198CFG_STM32_IWDG ?= y 199CFG_STM32_RNG ?= y 200CFG_STM32_RSTCTRL ?= y 201CFG_STM32_SAES ?= y 202CFG_STM32_TAMP ?= y 203CFG_STM32_UART ?= y 204CFG_STPMIC1 ?= y 205CFG_TZC400 ?= y 206 207CFG_WITH_SOFTWARE_PRNG ?= n 208ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 209$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 210endif 211 212ifeq ($(CFG_STPMIC1),y) 213$(call force,CFG_STM32_I2C,y) 214$(call force,CFG_STM32_GPIO,y) 215endif 216 217# If any crypto driver is enabled, enable the crypto-framework layer 218ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y) 219$(call force,CFG_STM32_CRYPTO_DRIVER,y) 220endif 221 222CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 223$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 224 225CFG_WDT ?= $(CFG_STM32_IWDG) 226 227# Platform specific configuration 228CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 229 230# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 231ifneq ($(CFG_SCMI_SCPFW),y) 232CFG_SCMI_MSG_DRIVERS ?= y 233endif 234 235# SiP/OEM service for non-secure world 236CFG_STM32_BSEC_SIP ?= n 237CFG_STM32MP1_SCMI_SIP ?= n 238ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 239$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 240$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 241$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 242endif 243 244# Enable BSEC PTA for fuses access management 245CFG_STM32_BSEC_PTA ?= y 246ifeq ($(CFG_STM32_BSEC_PTA),y) 247$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 248endif 249 250# Default enable SCMI PTA support 251CFG_SCMI_PTA ?= y 252ifeq ($(CFG_SCMI_PTA),y) 253ifneq ($(CFG_SCMI_SCPFW),y) 254$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 255CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 256CFG_SCMI_MSG_SHM_MSG ?= y 257CFG_SCMI_MSG_SMT ?= y 258endif # !CFG_SCMI_SCPFW 259endif # CFG_SCMI_PTA 260 261CFG_SCMI_SCPFW ?= n 262ifeq ($(CFG_SCMI_SCPFW),y) 263$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1) 264endif 265 266CFG_SCMI_MSG_DRIVERS ?= n 267ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 268$(call force,CFG_SCMI_MSG_CLOCK,y) 269$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 270CFG_SCMI_MSG_SHM_MSG ?= y 271CFG_SCMI_MSG_SMT ?= y 272CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 273$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 274endif 275 276ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 277CFG_HWRNG_PTA ?= y 278endif 279ifeq ($(CFG_HWRNG_PTA),y) 280$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 281$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 282$(call force,CFG_HWRNG_QUALITY,1024) 283endif 284 285# Provision enough threads to pass xtest 286ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 287ifeq ($(CFG_WITH_PAGER),y) 288CFG_NUM_THREADS ?= 3 289else 290CFG_NUM_THREADS ?= 10 291endif 292endif 293 294# Default enable some test facitilites 295CFG_ENABLE_EMBEDDED_TESTS ?= y 296CFG_WITH_STATS ?= y 297 298# Enable OTP update with BSEC driver 299CFG_STM32_BSEC_WRITE ?= y 300 301# Default disable some support for pager memory size constraint 302ifeq ($(CFG_WITH_PAGER),y) 303CFG_TEE_CORE_DEBUG ?= n 304CFG_UNWIND ?= n 305CFG_LOCKDEP ?= n 306CFG_TA_BGET_TEST ?= n 307# Default disable early TA compression to support a smaller HEAP size 308CFG_EARLY_TA_COMPRESS ?= n 309CFG_CORE_HEAP_SIZE ?= 49152 310endif 311 312# Non-secure UART and GPIO/pinctrl for the output console 313CFG_WITH_NSEC_GPIOS ?= y 314CFG_WITH_NSEC_UARTS ?= y 315# UART instance used for early console (0 disables early console) 316CFG_STM32_EARLY_CONSOLE_UART ?= 4 317 318# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 319# Disable the HUK by default as it requires a product specific configuration. 320# 321# Configuration must provide OTP indices where HUK is loaded. 322# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 323# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 324# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 325# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 326# 327# Configuration must provide the HUK generation scheme. The following switches 328# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 329# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 330# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 331# content derived with the device UID fuses content. See derivation scheme 332# in stm32mp15_huk.c implementation. 333CFG_STM32MP15_HUK ?= n 334CFG_STM32_HUK_FROM_DT ?= n 335 336ifeq ($(CFG_STM32MP15_HUK),y) 337ifneq ($(CFG_STM32_HUK_FROM_DT),y) 338ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 339$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 340$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 341$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 342$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 343endif 344ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 345$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 346endif 347ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 348$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 349endif 350ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 351$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 352endif 353ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 354$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 355endif 356endif # CFG_STM32_HUK_FROM_DT 357 358CFG_STM32MP15_HUK_BSEC_KEY ?= y 359CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 360ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 361$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 362else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 363$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 364endif 365endif # CFG_STM32MP15_HUK 366 367CFG_TEE_CORE_DEBUG ?= y 368CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 369 370# Sanity on choice config switches 371ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 372$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 373endif 374