1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8flavor_dts_file-157A_DK1_SCMI = stm32mp157a-dk1-scmi.dts 9flavor_dts_file-157C_DK2_SCMI = stm32mp157c-dk2-scmi.dts 10flavor_dts_file-157C_ED1_SCMI = stm32mp157c-ed1-scmi.dts 11flavor_dts_file-157C_EV1_SCMI = stm32mp157c-ev1-scmi.dts 12 13flavor_dts_file-135F_DK = stm32mp135f-dk.dts 14 15flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 16 $(flavor_dts_file-157C_DK2_SCMI) \ 17 $(flavor_dts_file-135F_DK) 18 19flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) \ 20 $(flavor_dts_file-157A_DK1_SCMI) 21 22flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 23 $(flavor_dts_file-157C_ED1) \ 24 $(flavor_dts_file-157C_EV1) \ 25 $(flavor_dts_file-157C_ED1_SCMI) \ 26 $(flavor_dts_file-157C_EV1_SCMI) 27 28flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 29 30flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 31 $(flavorlist-no_cryp-1G) 32 33flavorlist-512M = $(flavorlist-cryp-512M) \ 34 $(flavorlist-no_cryp-512M) 35 36flavorlist-1G = $(flavorlist-cryp-1G) \ 37 $(flavorlist-no_cryp-1G) 38 39flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 40 $(flavor_dts_file-157C_DK2) \ 41 $(flavor_dts_file-157C_ED1) \ 42 $(flavor_dts_file-157C_EV1) \ 43 $(flavor_dts_file-157A_DK1_SCMI) \ 44 $(flavor_dts_file-157C_DK2_SCMI) \ 45 $(flavor_dts_file-157C_ED1_SCMI) \ 46 $(flavor_dts_file-157C_EV1_SCMI) 47 48flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 49 $(flavor_dts_file-157A_DK1) \ 50 $(flavor_dts_file-157C_DHCOM_PDK2) \ 51 $(flavor_dts_file-157C_DK2) \ 52 $(flavor_dts_file-157C_ED1) \ 53 $(flavor_dts_file-157C_EV1) \ 54 $(flavor_dts_file-157A_DK1_SCMI) \ 55 $(flavor_dts_file-157C_DK2_SCMI) \ 56 $(flavor_dts_file-157C_ED1_SCMI) \ 57 $(flavor_dts_file-157C_EV1_SCMI) 58 59flavorlist-MP13 = $(flavor_dts_file-135F_DK) 60 61flavorlist-dh-platforms = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 62 $(flavor_dts_file-157C_DHCOM_PDK2) 63 64ifneq ($(PLATFORM_FLAVOR),) 65ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 66$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 67endif 68CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 69endif 70CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 71 72ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 73$(call force,CFG_STM32_CRYP,n) 74$(call force,CFG_STM32_SAES,n) 75endif 76 77ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 78$(call force,CFG_HWRNG_PTA,n) 79$(call force,CFG_WITH_SOFTWARE_PRNG,y) 80endif 81 82ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 83CFG_STM32MP15_HUK ?= y 84CFG_STM32_HUK_FROM_DT ?= y 85endif 86 87ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 88$(call force,CFG_STM32MP13,y) 89endif 90 91ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 92$(call force,CFG_STM32MP15,y) 93endif 94 95ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-dh-platforms)),) 96CFG_STM32_ALLOW_UNSAFE_PROBE ?= y 97endif 98 99# CFG_STM32MP1x switches are exclusive. 100# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 101# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 102ifeq ($(CFG_STM32MP13),y) 103$(call force,CFG_STM32MP15,n) 104else 105$(call force,CFG_STM32MP15,y) 106$(call force,CFG_STM32MP13,n) 107endif 108ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 109$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 110endif 111ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 112$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 113endif 114 115include core/arch/arm/cpu/cortex-a7.mk 116 117$(call force,CFG_DRIVERS_CLK,y) 118$(call force,CFG_DRIVERS_CLK_DT,y) 119$(call force,CFG_DRIVERS_GPIO,y) 120$(call force,CFG_DRIVERS_PINCTRL,y) 121$(call force,CFG_DRIVERS_REGULATOR,y) 122$(call force,CFG_GIC,y) 123$(call force,CFG_INIT_CNTVOFF,y) 124$(call force,CFG_PSCI_ARM32,y) 125$(call force,CFG_REGULATOR_FIXED,y) 126$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 127$(call force,CFG_SM_PLATFORM_HANDLER,y) 128$(call force,CFG_STM32_SHARED_IO,y) 129 130ifeq ($(CFG_STM32MP13),y) 131$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 132$(call force,CFG_CORE_ASYNC_NOTIF,y) 133$(call force,CFG_CORE_ASYNC_NOTIF_GIC_INTID,31) 134$(call force,CFG_CORE_RESERVED_SHM,n) 135$(call force,CFG_DRIVERS_CLK_FIXED,y) 136$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 137$(call force,CFG_STM32_GPIO,y) 138$(call force,CFG_STM32_VREFBUF,y) 139$(call force,CFG_STM32MP_CLK_CORE,y) 140$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 141$(call force,CFG_STM32MP1_RSTCTRL,y) 142$(call force,CFG_STM32MP13_CLK,y) 143$(call force,CFG_STM32MP13_REGULATOR_IOD,y) 144$(call force,CFG_TEE_CORE_NB_CORE,1) 145$(call force,CFG_WITH_NSEC_GPIOS,n) 146CFG_EXTERNAL_DT ?= n 147CFG_STM32MP_OPP_COUNT ?= 2 148CFG_WITH_PAGER ?= n 149endif # CFG_STM32MP13 150 151ifeq ($(CFG_STM32MP15),y) 152$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 153$(call force,CFG_DRIVERS_CLK_FIXED,n) 154$(call force,CFG_HALT_CORES_ON_PANIC_SGI,15) 155$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 156$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 157$(call force,CFG_STM32_SAES,n) 158$(call force,CFG_STM32MP1_RSTCTRL,y) 159$(call force,CFG_STM32MP15_CLK,y) 160CFG_CORE_RESERVED_SHM ?= n 161CFG_HALT_CORES_ON_PANIC ?= y 162CFG_EXTERNAL_DT ?= y 163CFG_STM32_BSEC_SIP ?= y 164CFG_TEE_CORE_NB_CORE ?= 2 165CFG_WITH_PAGER ?= y 166CFG_WITH_SOFTWARE_PRNG ?= y 167endif # CFG_STM32MP15 168 169ifeq ($(CFG_WITH_PAGER),y) 170CFG_WITH_LPAE ?= n 171endif 172CFG_WITH_LPAE ?= y 173CFG_MMAP_REGIONS ?= 23 174CFG_DTB_MAX_SIZE ?= (256 * 1024) 175CFG_CORE_ASLR ?= n 176 177CFG_STM32MP_REMOTEPROC ?= n 178CFG_DRIVERS_REMOTEPROC ?= $(CFG_STM32MP_REMOTEPROC) 179CFG_REMOTEPROC_PTA ?= $(CFG_STM32MP_REMOTEPROC) 180ifeq ($(CFG_REMOTEPROC_PTA),y) 181# Remoteproc early TA for coprocessor firmware management in boot stages 182CFG_IN_TREE_EARLY_TAS += remoteproc/80a4c275-0a47-4905-8285-1486a9771a08 183# Embed public part of this key in OP-TEE OS 184RPROC_SIGN_KEY ?= keys/default.pem 185endif 186 187ifneq ($(CFG_WITH_LPAE),y) 188# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 189CFG_TEE_RAM_VA_SIZE ?= 0x00200000 190endif 191 192ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 193CFG_TZDRAM_START ?= 0xde000000 194CFG_DRAM_SIZE ?= 0x20000000 195endif 196 197CFG_DRAM_BASE ?= 0xc0000000 198CFG_DRAM_SIZE ?= 0x40000000 199 200# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 201# device memory mapped SRAM used for SCMI message transfers. 202# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 203# native shared memory for SCMI communication instead of SRAM. 204# 205# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 206# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 207# disabled. 208CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 209ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 210$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 211CFG_TZSRAM_SIZE ?= 0x0003f000 212else 213CFG_STM32MP1_SCMI_SHM_BASE ?= 0 214endif 215$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 216 217ifeq ($(CFG_STM32MP15),y) 218CFG_TZDRAM_START ?= 0xfe000000 219ifeq ($(CFG_CORE_RESERVED_SHM),y) 220CFG_TZDRAM_SIZE ?= 0x01e00000 221else 222CFG_TZDRAM_SIZE ?= 0x02000000 223endif 224CFG_TZSRAM_START ?= 0x2ffc0000 225CFG_TZSRAM_SIZE ?= 0x00040000 226ifeq ($(CFG_CORE_RESERVED_SHM),y) 227CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 228CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 229endif 230else 231CFG_TZDRAM_SIZE ?= 0x02000000 232CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 233endif #CFG_STM32MP15 234 235CFG_STM32_BSEC ?= y 236CFG_STM32_CRYP ?= y 237CFG_STM32_ETZPC ?= y 238CFG_STM32_GPIO ?= y 239CFG_STM32_I2C ?= y 240CFG_STM32_IWDG ?= y 241CFG_STM32_RNG ?= y 242CFG_STM32_RSTCTRL ?= y 243CFG_STM32_SAES ?= y 244CFG_STM32_TAMP ?= y 245CFG_STM32_UART ?= y 246CFG_STPMIC1 ?= y 247CFG_TZC400 ?= y 248 249CFG_DRIVERS_I2C ?= $(CFG_STM32_I2C) 250CFG_REGULATOR_GPIO ?= $(CFG_STM32_GPIO) 251 252CFG_WITH_SOFTWARE_PRNG ?= n 253ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 254$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 255endif 256 257ifeq ($(CFG_STPMIC1),y) 258$(call force,CFG_STM32_I2C,y) 259$(call force,CFG_STM32_GPIO,y) 260endif 261 262# If any crypto driver is enabled, enable the crypto-framework layer 263ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y) 264$(call force,CFG_STM32_CRYPTO_DRIVER,y) 265endif 266 267CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 268$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 269 270CFG_WDT ?= $(CFG_STM32_IWDG) 271CFG_WDT_SM_HANDLER ?= $(CFG_WDT) 272CFG_WDT_SM_HANDLER_ID ?= 0xbc000000 273$(eval $(call cfg-depends-all,CFG_STM32_IWDG,CFG_WDT_SM_HANDLER CFG_WDT)) 274 275# Platform specific configuration 276CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 277 278# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 279ifneq ($(CFG_SCMI_SCPFW),y) 280CFG_SCMI_MSG_DRIVERS ?= y 281endif 282 283# SiP/OEM service for non-secure world 284CFG_STM32_BSEC_SIP ?= n 285CFG_STM32MP1_SCMI_SIP ?= n 286ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 287$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 288$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 289$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 290endif 291 292# Enable BSEC PTA for fuses access management 293CFG_STM32_BSEC_PTA ?= y 294ifeq ($(CFG_STM32_BSEC_PTA),y) 295$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 296endif 297 298# Default enable SCMI PTA support 299CFG_SCMI_PTA ?= y 300ifeq ($(CFG_SCMI_PTA),y) 301ifneq ($(CFG_SCMI_SCPFW),y) 302$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 303CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 304CFG_SCMI_MSG_SHM_MSG ?= y 305CFG_SCMI_MSG_SMT ?= y 306endif # !CFG_SCMI_SCPFW 307endif # CFG_SCMI_PTA 308 309CFG_SCMI_SCPFW ?= n 310ifeq ($(CFG_SCMI_SCPFW),y) 311$(call force,CFG_SCMI_SCPFW_PRODUCT,stm32mp1) 312endif 313 314CFG_SCMI_MSG_DRIVERS ?= n 315ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 316$(call force,CFG_SCMI_MSG_CLOCK,y) 317$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 318CFG_SCMI_MSG_SHM_MSG ?= y 319CFG_SCMI_MSG_SMT ?= y 320CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 321$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 322endif 323 324ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 325CFG_HWRNG_PTA ?= y 326endif 327ifeq ($(CFG_HWRNG_PTA),y) 328$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 329$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 330$(call force,CFG_HWRNG_QUALITY,1024) 331endif 332 333# Provision enough threads to pass xtest 334ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 335ifeq ($(CFG_WITH_PAGER),y) 336CFG_NUM_THREADS ?= 3 337else 338CFG_NUM_THREADS ?= 10 339endif 340endif 341 342# Default enable some test facitilites 343CFG_ENABLE_EMBEDDED_TESTS ?= y 344CFG_WITH_STATS ?= y 345 346# Default enable software fallback on crypto drivers 347CFG_STM32_SAES_SW_FALLBACK ?= y 348 349# Enable OTP update with BSEC driver 350CFG_STM32_BSEC_WRITE ?= y 351 352# Default disable some support for pager memory size constraint 353ifeq ($(CFG_WITH_PAGER),y) 354CFG_TEE_CORE_DEBUG ?= n 355CFG_UNWIND ?= n 356CFG_LOCKDEP ?= n 357CFG_TA_BGET_TEST ?= n 358endif 359 360# Non-secure UART and GPIO/pinctrl for the output console 361CFG_WITH_NSEC_GPIOS ?= y 362CFG_WITH_NSEC_UARTS ?= y 363# UART instance used for early console (0 disables early console) 364CFG_STM32_EARLY_CONSOLE_UART ?= 4 365 366# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 367# Disable the HUK by default as it requires a product specific configuration. 368# 369# Configuration must provide OTP indices where HUK is loaded. 370# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 371# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 372# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 373# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 374# 375# Configuration must provide the HUK generation scheme. The following switches 376# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 377# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 378# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 379# content derived with the device UID fuses content. See derivation scheme 380# in stm32mp15_huk.c implementation. 381CFG_STM32MP15_HUK ?= n 382CFG_STM32_HUK_FROM_DT ?= n 383 384ifeq ($(CFG_STM32MP15_HUK),y) 385ifneq ($(CFG_STM32_HUK_FROM_DT),y) 386ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 387$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 388$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 389$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 390$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 391endif 392ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 393$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 394endif 395ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 396$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 397endif 398ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 399$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 400endif 401ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 402$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 403endif 404endif # CFG_STM32_HUK_FROM_DT 405 406CFG_STM32MP15_HUK_BSEC_KEY ?= y 407CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 408ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 409$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 410else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 411$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 412endif 413endif # CFG_STM32MP15_HUK 414 415CFG_TEE_CORE_DEBUG ?= y 416CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 417 418# Sanity on choice config switches 419ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 420$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 421endif 422 423CFG_DRIVERS_FIREWALL ?= y 424ifeq ($(CFG_STM32_ETZPC),y) 425$(call force,CFG_DRIVERS_FIREWALL,y) 426endif 427 428# Allow probing of unsafe peripherals. Firewall config will not be checked 429CFG_STM32_ALLOW_UNSAFE_PROBE ?= n 430