1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8flavor_dts_file-157A_DK1_SCMI = stm32mp157a-dk1-scmi.dts 9flavor_dts_file-157C_DK2_SCMI = stm32mp157c-dk2-scmi.dts 10flavor_dts_file-157C_ED1_SCMI = stm32mp157c-ed1-scmi.dts 11flavor_dts_file-157C_EV1_SCMI = stm32mp157c-ev1-scmi.dts 12 13flavor_dts_file-135F_DK = stm32mp135f-dk.dts 14 15flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 16 $(flavor_dts_file-157C_DK2_SCMI) \ 17 $(flavor_dts_file-135F_DK) 18 19flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) \ 20 $(flavor_dts_file-157A_DK1_SCMI) 21 22flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 23 $(flavor_dts_file-157C_ED1) \ 24 $(flavor_dts_file-157C_EV1) \ 25 $(flavor_dts_file-157C_ED1_SCMI) \ 26 $(flavor_dts_file-157C_EV1_SCMI) 27 28flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 29 30flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 31 $(flavorlist-no_cryp-1G) 32 33flavorlist-512M = $(flavorlist-cryp-512M) \ 34 $(flavorlist-no_cryp-512M) 35 36flavorlist-1G = $(flavorlist-cryp-1G) \ 37 $(flavorlist-no_cryp-1G) 38 39flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 40 $(flavor_dts_file-157C_DK2) \ 41 $(flavor_dts_file-157C_ED1) \ 42 $(flavor_dts_file-157C_EV1) \ 43 $(flavor_dts_file-157A_DK1_SCMI) \ 44 $(flavor_dts_file-157C_DK2_SCMI) \ 45 $(flavor_dts_file-157C_ED1_SCMI) \ 46 $(flavor_dts_file-157C_EV1_SCMI) 47 48flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 49 $(flavor_dts_file-157A_DK1) \ 50 $(flavor_dts_file-157C_DHCOM_PDK2) \ 51 $(flavor_dts_file-157C_DK2) \ 52 $(flavor_dts_file-157C_ED1) \ 53 $(flavor_dts_file-157C_EV1) \ 54 $(flavor_dts_file-157A_DK1_SCMI) \ 55 $(flavor_dts_file-157C_DK2_SCMI) \ 56 $(flavor_dts_file-157C_ED1_SCMI) \ 57 $(flavor_dts_file-157C_EV1_SCMI) 58 59flavorlist-MP13 = $(flavor_dts_file-135F_DK) 60 61ifneq ($(PLATFORM_FLAVOR),) 62ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 63$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 64endif 65CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 66endif 67CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 68 69ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 70$(call force,CFG_STM32_CRYP,n) 71$(call force,CFG_STM32_SAES,n) 72endif 73 74ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 75$(call force,CFG_HWRNG_PTA,n) 76$(call force,CFG_WITH_SOFTWARE_PRNG,y) 77endif 78 79ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 80CFG_STM32MP15_HUK ?= y 81CFG_STM32_HUK_FROM_DT ?= y 82endif 83 84ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 85$(call force,CFG_STM32MP13,y) 86endif 87 88ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 89$(call force,CFG_STM32MP15,y) 90endif 91 92# CFG_STM32MP1x switches are exclusive. 93# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 94# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 95ifeq ($(CFG_STM32MP13),y) 96$(call force,CFG_STM32MP15,n) 97else 98$(call force,CFG_STM32MP15,y) 99$(call force,CFG_STM32MP13,n) 100endif 101ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 102$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 103endif 104ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 105$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 106endif 107 108include core/arch/arm/cpu/cortex-a7.mk 109 110$(call force,CFG_DRIVERS_CLK,y) 111$(call force,CFG_DRIVERS_CLK_DT,y) 112$(call force,CFG_DRIVERS_GPIO,y) 113$(call force,CFG_DRIVERS_PINCTRL,y) 114$(call force,CFG_DRIVERS_REGULATOR,y) 115$(call force,CFG_GIC,y) 116$(call force,CFG_INIT_CNTVOFF,y) 117$(call force,CFG_PSCI_ARM32,y) 118$(call force,CFG_REGULATOR_FIXED,y) 119$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 120$(call force,CFG_SM_PLATFORM_HANDLER,y) 121$(call force,CFG_STM32_SHARED_IO,y) 122 123ifeq ($(CFG_STM32MP13),y) 124$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 125$(call force,CFG_CORE_ASYNC_NOTIF,y) 126$(call force,CFG_CORE_ASYNC_NOTIF_GIC_INTID,31) 127$(call force,CFG_CORE_RESERVED_SHM,n) 128$(call force,CFG_DRIVERS_CLK_FIXED,y) 129$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 130$(call force,CFG_STM32_GPIO,y) 131$(call force,CFG_STM32_VREFBUF,y) 132$(call force,CFG_STM32MP_CLK_CORE,y) 133$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 134$(call force,CFG_STM32MP13_CLK,y) 135$(call force,CFG_STM32MP13_REGULATOR_IOD,y) 136$(call force,CFG_TEE_CORE_NB_CORE,1) 137$(call force,CFG_WITH_NSEC_GPIOS,n) 138CFG_EXTERNAL_DT ?= n 139CFG_STM32MP_OPP_COUNT ?= 2 140CFG_WITH_PAGER ?= n 141endif # CFG_STM32MP13 142 143ifeq ($(CFG_STM32MP15),y) 144$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 145$(call force,CFG_DRIVERS_CLK_FIXED,n) 146$(call force,CFG_HALT_CORES_ON_PANIC_SGI,15) 147$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 148$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 149$(call force,CFG_STM32_SAES,n) 150$(call force,CFG_STM32MP15_CLK,y) 151CFG_CORE_RESERVED_SHM ?= n 152CFG_HALT_CORES_ON_PANIC ?= y 153CFG_EXTERNAL_DT ?= y 154CFG_STM32_BSEC_SIP ?= y 155CFG_TEE_CORE_NB_CORE ?= 2 156CFG_WITH_PAGER ?= y 157CFG_WITH_SOFTWARE_PRNG ?= y 158endif # CFG_STM32MP15 159 160ifeq ($(CFG_WITH_PAGER),y) 161CFG_WITH_LPAE ?= n 162endif 163CFG_WITH_LPAE ?= y 164CFG_MMAP_REGIONS ?= 23 165CFG_DTB_MAX_SIZE ?= (256 * 1024) 166CFG_CORE_ASLR ?= n 167 168CFG_STM32MP_REMOTEPROC ?= n 169CFG_DRIVERS_REMOTEPROC ?= $(CFG_STM32MP_REMOTEPROC) 170CFG_REMOTEPROC_PTA ?= $(CFG_STM32MP_REMOTEPROC) 171ifeq ($(CFG_REMOTEPROC_PTA),y) 172# Remoteproc early TA for coprocessor firmware management in boot stages 173CFG_IN_TREE_EARLY_TAS += remoteproc/80a4c275-0a47-4905-8285-1486a9771a08 174# Embed public part of this key in OP-TEE OS 175RPROC_SIGN_KEY ?= keys/default.pem 176endif 177 178ifneq ($(CFG_WITH_LPAE),y) 179# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 180CFG_TEE_RAM_VA_SIZE ?= 0x00200000 181endif 182 183ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 184CFG_TZDRAM_START ?= 0xde000000 185CFG_DRAM_SIZE ?= 0x20000000 186endif 187 188CFG_DRAM_BASE ?= 0xc0000000 189CFG_DRAM_SIZE ?= 0x40000000 190 191# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 192# device memory mapped SRAM used for SCMI message transfers. 193# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 194# native shared memory for SCMI communication instead of SRAM. 195# 196# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 197# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 198# disabled. 199CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 200ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 201$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 202else 203CFG_STM32MP1_SCMI_SHM_BASE ?= 0 204endif 205$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 206 207ifeq ($(CFG_STM32MP15),y) 208CFG_TZDRAM_START ?= 0xfe000000 209ifeq ($(CFG_CORE_RESERVED_SHM),y) 210CFG_TZDRAM_SIZE ?= 0x01e00000 211else 212CFG_TZDRAM_SIZE ?= 0x02000000 213endif 214CFG_TZSRAM_START ?= 0x2ffc0000 215CFG_TZSRAM_SIZE ?= 0x0003f000 216ifeq ($(CFG_CORE_RESERVED_SHM),y) 217CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 218CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 219endif 220else 221CFG_TZDRAM_SIZE ?= 0x02000000 222CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 223endif #CFG_STM32MP15 224 225CFG_STM32_BSEC ?= y 226CFG_STM32_CRYP ?= y 227CFG_STM32_ETZPC ?= y 228CFG_STM32_GPIO ?= y 229CFG_STM32_I2C ?= y 230CFG_STM32_IWDG ?= y 231CFG_STM32_RNG ?= y 232CFG_STM32_RSTCTRL ?= y 233CFG_STM32_SAES ?= y 234CFG_STM32_TAMP ?= y 235CFG_STM32_UART ?= y 236CFG_STPMIC1 ?= y 237CFG_TZC400 ?= y 238 239CFG_DRIVERS_I2C ?= $(CFG_STM32_I2C) 240CFG_REGULATOR_GPIO ?= $(CFG_STM32_GPIO) 241 242CFG_WITH_SOFTWARE_PRNG ?= n 243ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 244$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 245endif 246 247ifeq ($(CFG_STPMIC1),y) 248$(call force,CFG_STM32_I2C,y) 249$(call force,CFG_STM32_GPIO,y) 250endif 251 252# If any crypto driver is enabled, enable the crypto-framework layer 253ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y) 254$(call force,CFG_STM32_CRYPTO_DRIVER,y) 255endif 256 257CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 258$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 259 260CFG_WDT ?= $(CFG_STM32_IWDG) 261CFG_WDT_SM_HANDLER ?= $(CFG_WDT) 262CFG_WDT_SM_HANDLER_ID ?= 0xbc000000 263 264# Platform specific configuration 265CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 266 267# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 268ifneq ($(CFG_SCMI_SCPFW),y) 269CFG_SCMI_MSG_DRIVERS ?= y 270endif 271 272# SiP/OEM service for non-secure world 273CFG_STM32_BSEC_SIP ?= n 274CFG_STM32MP1_SCMI_SIP ?= n 275ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 276$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 277$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 278$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 279endif 280 281# Enable BSEC PTA for fuses access management 282CFG_STM32_BSEC_PTA ?= y 283ifeq ($(CFG_STM32_BSEC_PTA),y) 284$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 285endif 286 287# Default enable SCMI PTA support 288CFG_SCMI_PTA ?= y 289ifeq ($(CFG_SCMI_PTA),y) 290ifneq ($(CFG_SCMI_SCPFW),y) 291$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 292CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 293CFG_SCMI_MSG_SHM_MSG ?= y 294CFG_SCMI_MSG_SMT ?= y 295endif # !CFG_SCMI_SCPFW 296endif # CFG_SCMI_PTA 297 298CFG_SCMI_SCPFW ?= n 299ifeq ($(CFG_SCMI_SCPFW),y) 300$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1) 301endif 302 303CFG_SCMI_MSG_DRIVERS ?= n 304ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 305$(call force,CFG_SCMI_MSG_CLOCK,y) 306$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 307CFG_SCMI_MSG_SHM_MSG ?= y 308CFG_SCMI_MSG_SMT ?= y 309CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 310$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 311endif 312 313ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 314CFG_HWRNG_PTA ?= y 315endif 316ifeq ($(CFG_HWRNG_PTA),y) 317$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 318$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 319$(call force,CFG_HWRNG_QUALITY,1024) 320endif 321 322# Provision enough threads to pass xtest 323ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 324ifeq ($(CFG_WITH_PAGER),y) 325CFG_NUM_THREADS ?= 3 326else 327CFG_NUM_THREADS ?= 10 328endif 329endif 330 331# Default enable some test facitilites 332CFG_ENABLE_EMBEDDED_TESTS ?= y 333CFG_WITH_STATS ?= y 334 335# Enable OTP update with BSEC driver 336CFG_STM32_BSEC_WRITE ?= y 337 338# Default disable some support for pager memory size constraint 339ifeq ($(CFG_WITH_PAGER),y) 340CFG_TEE_CORE_DEBUG ?= n 341CFG_UNWIND ?= n 342CFG_LOCKDEP ?= n 343CFG_TA_BGET_TEST ?= n 344# Default disable early TA compression to support a smaller HEAP size 345CFG_EARLY_TA_COMPRESS ?= n 346CFG_CORE_HEAP_SIZE ?= 49152 347endif 348 349# Non-secure UART and GPIO/pinctrl for the output console 350CFG_WITH_NSEC_GPIOS ?= y 351CFG_WITH_NSEC_UARTS ?= y 352# UART instance used for early console (0 disables early console) 353CFG_STM32_EARLY_CONSOLE_UART ?= 4 354 355# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 356# Disable the HUK by default as it requires a product specific configuration. 357# 358# Configuration must provide OTP indices where HUK is loaded. 359# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 360# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 361# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 362# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 363# 364# Configuration must provide the HUK generation scheme. The following switches 365# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 366# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 367# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 368# content derived with the device UID fuses content. See derivation scheme 369# in stm32mp15_huk.c implementation. 370CFG_STM32MP15_HUK ?= n 371CFG_STM32_HUK_FROM_DT ?= n 372 373ifeq ($(CFG_STM32MP15_HUK),y) 374ifneq ($(CFG_STM32_HUK_FROM_DT),y) 375ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 376$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 377$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 378$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 379$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 380endif 381ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 382$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 383endif 384ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 385$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 386endif 387ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 388$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 389endif 390ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 391$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 392endif 393endif # CFG_STM32_HUK_FROM_DT 394 395CFG_STM32MP15_HUK_BSEC_KEY ?= y 396CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 397ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 398$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 399else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 400$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 401endif 402endif # CFG_STM32MP15_HUK 403 404CFG_TEE_CORE_DEBUG ?= y 405CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 406 407# Sanity on choice config switches 408ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 409$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 410endif 411