1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 32 $(flavor_dts_file-157C_DK2) \ 33 $(flavor_dts_file-157C_ED1) \ 34 $(flavor_dts_file-157C_EV1) 35 36flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 37 $(flavor_dts_file-157A_DK1) \ 38 $(flavor_dts_file-157C_DHCOM_PDK2) \ 39 $(flavor_dts_file-157C_DK2) \ 40 $(flavor_dts_file-157C_ED1) \ 41 $(flavor_dts_file-157C_EV1) 42 43flavorlist-MP13 = $(flavor_dts_file-135F_DK) 44 45ifneq ($(PLATFORM_FLAVOR),) 46ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 47$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 48endif 49CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 50endif 51CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 52 53ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 54$(call force,CFG_STM32_CRYP,n) 55$(call force,CFG_STM32_SAES,n) 56endif 57 58ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 59$(call force,CFG_HWRNG_PTA,n) 60$(call force,CFG_WITH_SOFTWARE_PRNG,y) 61endif 62 63ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 64CFG_STM32MP15_HUK ?= y 65CFG_STM32_HUK_FROM_DT ?= y 66endif 67 68ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 69$(call force,CFG_STM32MP13,y) 70endif 71 72ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 73$(call force,CFG_STM32MP15,y) 74endif 75 76# CFG_STM32MP1x switches are exclusive. 77# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 78# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 79ifeq ($(CFG_STM32MP13),y) 80$(call force,CFG_STM32MP15,n) 81else 82$(call force,CFG_STM32MP15,y) 83$(call force,CFG_STM32MP13,n) 84endif 85ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 86$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 87endif 88ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 89$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 90endif 91 92include core/arch/arm/cpu/cortex-a7.mk 93 94$(call force,CFG_DRIVERS_CLK,y) 95$(call force,CFG_DRIVERS_CLK_DT,y) 96$(call force,CFG_DRIVERS_GPIO,y) 97$(call force,CFG_DRIVERS_PINCTRL,y) 98$(call force,CFG_GIC,y) 99$(call force,CFG_INIT_CNTVOFF,y) 100$(call force,CFG_PSCI_ARM32,y) 101$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 102$(call force,CFG_SM_PLATFORM_HANDLER,y) 103$(call force,CFG_STM32_SHARED_IO,y) 104 105ifeq ($(CFG_STM32MP13),y) 106$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 107$(call force,CFG_CORE_RESERVED_SHM,n) 108$(call force,CFG_DRIVERS_CLK_FIXED,y) 109$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 110$(call force,CFG_STM32_GPIO,y) 111$(call force,CFG_STM32MP_CLK_CORE,y) 112$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 113$(call force,CFG_STM32MP13_CLK,y) 114$(call force,CFG_TEE_CORE_NB_CORE,1) 115$(call force,CFG_WITH_NSEC_GPIOS,n) 116CFG_EXTERNAL_DT ?= n 117CFG_STM32MP_OPP_COUNT ?= 2 118CFG_STM32MP1_SCMI_SHM_SYSRAM ?= y 119CFG_WITH_PAGER ?= n 120endif # CFG_STM32MP13 121 122ifeq ($(CFG_STM32MP15),y) 123$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 124$(call force,CFG_DRIVERS_CLK_FIXED,n) 125$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 126$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 127$(call force,CFG_STM32_SAES,n) 128$(call force,CFG_STM32MP15_CLK,y) 129CFG_CORE_RESERVED_SHM ?= y 130CFG_EXTERNAL_DT ?= y 131CFG_STM32_BSEC_SIP ?= y 132CFG_TEE_CORE_NB_CORE ?= 2 133CFG_WITH_PAGER ?= y 134CFG_WITH_SOFTWARE_PRNG ?= y 135endif # CFG_STM32MP15 136 137ifeq ($(CFG_WITH_PAGER),y) 138CFG_WITH_LPAE ?= n 139endif 140CFG_WITH_LPAE ?= y 141CFG_MMAP_REGIONS ?= 23 142CFG_DTB_MAX_SIZE ?= (256 * 1024) 143CFG_CORE_ASLR ?= n 144 145ifneq ($(CFG_WITH_LPAE),y) 146# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 147CFG_TEE_RAM_VA_SIZE ?= 0x00200000 148endif 149 150ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 151CFG_TZDRAM_START ?= 0xde000000 152CFG_DRAM_SIZE ?= 0x20000000 153endif 154 155CFG_DRAM_BASE ?= 0xc0000000 156CFG_DRAM_SIZE ?= 0x40000000 157 158# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 159# device memory mapped SRAM used for SCMI message transfers. 160# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 161# native shared memory for SCMI communication instead of SRAM. 162# 163# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 164# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 165# disabled. 166CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 167ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 168$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 169else 170CFG_STM32MP1_SCMI_SHM_BASE ?= 0 171endif 172$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 173 174ifeq ($(CFG_STM32MP15),y) 175CFG_TZDRAM_START ?= 0xfe000000 176ifeq ($(CFG_CORE_RESERVED_SHM),y) 177CFG_TZDRAM_SIZE ?= 0x01e00000 178else 179CFG_TZDRAM_SIZE ?= 0x02000000 180endif 181CFG_TZSRAM_START ?= 0x2ffc0000 182CFG_TZSRAM_SIZE ?= 0x0003f000 183ifeq ($(CFG_CORE_RESERVED_SHM),y) 184CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 185CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 186endif 187else 188CFG_TZDRAM_SIZE ?= 0x02000000 189CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 190endif #CFG_STM32MP15 191 192CFG_STM32_BSEC ?= y 193CFG_STM32_CRYP ?= y 194CFG_STM32_ETZPC ?= y 195CFG_STM32_GPIO ?= y 196CFG_STM32_I2C ?= y 197CFG_STM32_IWDG ?= y 198CFG_STM32_RNG ?= y 199CFG_STM32_RSTCTRL ?= y 200CFG_STM32_SAES ?= y 201CFG_STM32_TAMP ?= y 202CFG_STM32_UART ?= y 203CFG_STPMIC1 ?= y 204CFG_TZC400 ?= y 205 206CFG_WITH_SOFTWARE_PRNG ?= n 207ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 208$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 209endif 210 211ifeq ($(CFG_STPMIC1),y) 212$(call force,CFG_STM32_I2C,y) 213$(call force,CFG_STM32_GPIO,y) 214endif 215 216# If any crypto driver is enabled, enable the crypto-framework layer 217ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y) 218$(call force,CFG_STM32_CRYPTO_DRIVER,y) 219endif 220 221CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 222$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 223 224CFG_WDT ?= $(CFG_STM32_IWDG) 225 226# Platform specific configuration 227CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 228 229# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 230ifneq ($(CFG_SCMI_SCPFW),y) 231CFG_SCMI_MSG_DRIVERS ?= y 232endif 233 234# SiP/OEM service for non-secure world 235CFG_STM32_BSEC_SIP ?= n 236CFG_STM32MP1_SCMI_SIP ?= n 237ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 238$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 239$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 240$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 241endif 242 243# Enable BSEC PTA for fuses access management 244CFG_STM32_BSEC_PTA ?= y 245ifeq ($(CFG_STM32_BSEC_PTA),y) 246$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 247endif 248 249# Default enable SCMI PTA support 250CFG_SCMI_PTA ?= y 251ifeq ($(CFG_SCMI_PTA),y) 252ifneq ($(CFG_SCMI_SCPFW),y) 253$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 254CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 255CFG_SCMI_MSG_SHM_MSG ?= y 256CFG_SCMI_MSG_SMT ?= y 257endif # !CFG_SCMI_SCPFW 258endif # CFG_SCMI_PTA 259 260CFG_SCMI_SCPFW ?= n 261ifeq ($(CFG_SCMI_SCPFW),y) 262$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1) 263endif 264 265CFG_SCMI_MSG_DRIVERS ?= n 266ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 267$(call force,CFG_SCMI_MSG_CLOCK,y) 268$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 269CFG_SCMI_MSG_SHM_MSG ?= y 270CFG_SCMI_MSG_SMT ?= y 271CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 272$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 273endif 274 275ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 276CFG_HWRNG_PTA ?= y 277endif 278ifeq ($(CFG_HWRNG_PTA),y) 279$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 280$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 281$(call force,CFG_HWRNG_QUALITY,1024) 282endif 283 284# Provision enough threads to pass xtest 285ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 286ifeq ($(CFG_WITH_PAGER),y) 287CFG_NUM_THREADS ?= 3 288else 289CFG_NUM_THREADS ?= 10 290endif 291endif 292 293# Default enable some test facitilites 294CFG_ENABLE_EMBEDDED_TESTS ?= y 295CFG_WITH_STATS ?= y 296 297# Enable OTP update with BSEC driver 298CFG_STM32_BSEC_WRITE ?= y 299 300# Default disable some support for pager memory size constraint 301ifeq ($(CFG_WITH_PAGER),y) 302CFG_TEE_CORE_DEBUG ?= n 303CFG_UNWIND ?= n 304CFG_LOCKDEP ?= n 305CFG_TA_BGET_TEST ?= n 306# Default disable early TA compression to support a smaller HEAP size 307CFG_EARLY_TA_COMPRESS ?= n 308CFG_CORE_HEAP_SIZE ?= 49152 309endif 310 311# Non-secure UART and GPIO/pinctrl for the output console 312CFG_WITH_NSEC_GPIOS ?= y 313CFG_WITH_NSEC_UARTS ?= y 314# UART instance used for early console (0 disables early console) 315CFG_STM32_EARLY_CONSOLE_UART ?= 4 316 317# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 318# Disable the HUK by default as it requires a product specific configuration. 319# 320# Configuration must provide OTP indices where HUK is loaded. 321# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 322# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 323# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 324# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 325# 326# Configuration must provide the HUK generation scheme. The following switches 327# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 328# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 329# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 330# content derived with the device UID fuses content. See derivation scheme 331# in stm32mp15_huk.c implementation. 332CFG_STM32MP15_HUK ?= n 333CFG_STM32_HUK_FROM_DT ?= n 334 335ifeq ($(CFG_STM32MP15_HUK),y) 336ifneq ($(CFG_STM32_HUK_FROM_DT),y) 337ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 338$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 339$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 340$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 341$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 342endif 343ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 344$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 345endif 346ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 347$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 348endif 349ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 350$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 351endif 352ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 353$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 354endif 355endif # CFG_STM32_HUK_FROM_DT 356 357CFG_STM32MP15_HUK_BSEC_KEY ?= y 358CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 359ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 360$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 361else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 362$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 363endif 364endif # CFG_STM32MP15_HUK 365 366CFG_TEE_CORE_DEBUG ?= y 367CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 368 369# Sanity on choice config switches 370ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 371$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 372endif 373