1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 32 $(flavor_dts_file-157C_DK2) \ 33 $(flavor_dts_file-157C_ED1) \ 34 $(flavor_dts_file-157C_EV1) 35 36flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 37 $(flavor_dts_file-157A_DK1) \ 38 $(flavor_dts_file-157C_DHCOM_PDK2) \ 39 $(flavor_dts_file-157C_DK2) \ 40 $(flavor_dts_file-157C_ED1) \ 41 $(flavor_dts_file-157C_EV1) 42 43flavorlist-MP13 = $(flavor_dts_file-135F_DK) 44 45ifneq ($(PLATFORM_FLAVOR),) 46ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 47$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 48endif 49CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 50endif 51CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 52 53ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 54$(call force,CFG_STM32_CRYP,n) 55endif 56 57ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 58$(call force,CFG_HWRNG_PTA,n) 59$(call force,CFG_WITH_SOFTWARE_PRNG,y) 60endif 61 62ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 63CFG_STM32MP15_HUK ?= y 64CFG_STM32_HUK_FROM_DT ?= y 65endif 66 67ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 68$(call force,CFG_STM32MP13,y) 69endif 70 71ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 72$(call force,CFG_STM32MP15,y) 73endif 74 75# CFG_STM32MP1x switches are exclusive. 76# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 77# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 78ifeq ($(CFG_STM32MP13),y) 79$(call force,CFG_STM32MP15,n) 80else 81$(call force,CFG_STM32MP15,y) 82$(call force,CFG_STM32MP13,n) 83endif 84ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 85$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 86endif 87ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 88$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 89endif 90 91include core/arch/arm/cpu/cortex-a7.mk 92 93$(call force,CFG_DRIVERS_CLK,y) 94$(call force,CFG_DRIVERS_CLK_DT,y) 95$(call force,CFG_DRIVERS_GPIO,y) 96$(call force,CFG_DRIVERS_PINCTRL,y) 97$(call force,CFG_GIC,y) 98$(call force,CFG_INIT_CNTVOFF,y) 99$(call force,CFG_PSCI_ARM32,y) 100$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 101$(call force,CFG_SM_PLATFORM_HANDLER,y) 102$(call force,CFG_STM32_SHARED_IO,y) 103 104ifeq ($(CFG_STM32MP13),y) 105$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 106$(call force,CFG_CORE_RESERVED_SHM,n) 107$(call force,CFG_DRIVERS_CLK_FIXED,y) 108$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 109$(call force,CFG_STM32_GPIO,y) 110$(call force,CFG_STM32MP_CLK_CORE,y) 111$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 112$(call force,CFG_STM32MP13_CLK,y) 113$(call force,CFG_TEE_CORE_NB_CORE,1) 114$(call force,CFG_WITH_NSEC_GPIOS,n) 115CFG_EXTERNAL_DT ?= n 116CFG_STM32MP_OPP_COUNT ?= 2 117CFG_STM32MP1_SCMI_SHM_SYSRAM ?= y 118CFG_WITH_PAGER ?= n 119endif # CFG_STM32MP13 120 121ifeq ($(CFG_STM32MP15),y) 122$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 123$(call force,CFG_DRIVERS_CLK_FIXED,n) 124$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 125$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 126$(call force,CFG_STM32MP15_CLK,y) 127CFG_CORE_RESERVED_SHM ?= y 128CFG_EXTERNAL_DT ?= y 129CFG_STM32_BSEC_SIP ?= y 130CFG_TEE_CORE_NB_CORE ?= 2 131CFG_WITH_PAGER ?= y 132CFG_WITH_SOFTWARE_PRNG ?= y 133endif # CFG_STM32MP15 134 135ifeq ($(CFG_WITH_PAGER),y) 136CFG_WITH_LPAE ?= n 137endif 138CFG_WITH_LPAE ?= y 139CFG_MMAP_REGIONS ?= 23 140CFG_DTB_MAX_SIZE ?= (256 * 1024) 141CFG_CORE_ASLR ?= n 142 143ifneq ($(CFG_WITH_LPAE),y) 144# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 145CFG_TEE_RAM_VA_SIZE ?= 0x00200000 146endif 147 148ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 149CFG_TZDRAM_START ?= 0xde000000 150CFG_DRAM_SIZE ?= 0x20000000 151endif 152 153CFG_DRAM_BASE ?= 0xc0000000 154CFG_DRAM_SIZE ?= 0x40000000 155 156# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 157# device memory mapped SRAM used for SCMI message transfers. 158# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 159# native shared memory for SCMI communication instead of SRAM. 160# 161# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 162# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 163# disabled. 164CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 165ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 166$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 167else 168CFG_STM32MP1_SCMI_SHM_BASE ?= 0 169endif 170$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 171 172ifeq ($(CFG_STM32MP15),y) 173CFG_TZDRAM_START ?= 0xfe000000 174ifeq ($(CFG_CORE_RESERVED_SHM),y) 175CFG_TZDRAM_SIZE ?= 0x01e00000 176else 177CFG_TZDRAM_SIZE ?= 0x02000000 178endif 179CFG_TZSRAM_START ?= 0x2ffc0000 180CFG_TZSRAM_SIZE ?= 0x0003f000 181ifeq ($(CFG_CORE_RESERVED_SHM),y) 182CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 183CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 184endif 185else 186CFG_TZDRAM_SIZE ?= 0x02000000 187CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 188endif #CFG_STM32MP15 189 190CFG_STM32_BSEC ?= y 191CFG_STM32_CRYP ?= y 192CFG_STM32_ETZPC ?= y 193CFG_STM32_GPIO ?= y 194CFG_STM32_I2C ?= y 195CFG_STM32_IWDG ?= y 196CFG_STM32_RNG ?= y 197CFG_STM32_RSTCTRL ?= y 198CFG_STM32_TAMP ?= y 199CFG_STM32_UART ?= y 200CFG_STPMIC1 ?= y 201CFG_TZC400 ?= y 202 203CFG_WITH_SOFTWARE_PRNG ?= n 204ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 205$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 206endif 207 208ifeq ($(CFG_STPMIC1),y) 209$(call force,CFG_STM32_I2C,y) 210$(call force,CFG_STM32_GPIO,y) 211endif 212 213# if any crypto driver is enabled, enable the crypto-framework layer 214ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 215$(call force,CFG_STM32_CRYPTO_DRIVER,y) 216endif 217 218CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 219$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 220 221CFG_WDT ?= $(CFG_STM32_IWDG) 222 223# Platform specific configuration 224CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 225 226# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 227ifneq ($(CFG_SCMI_SCPFW),y) 228CFG_SCMI_MSG_DRIVERS ?= y 229endif 230 231# SiP/OEM service for non-secure world 232CFG_STM32_BSEC_SIP ?= n 233CFG_STM32MP1_SCMI_SIP ?= n 234ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 235$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 236$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 237$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 238endif 239 240# Enable BSEC PTA for fuses access management 241CFG_STM32_BSEC_PTA ?= y 242ifeq ($(CFG_STM32_BSEC_PTA),y) 243$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 244endif 245 246# Default enable SCMI PTA support 247CFG_SCMI_PTA ?= y 248ifeq ($(CFG_SCMI_PTA),y) 249ifneq ($(CFG_SCMI_SCPFW),y) 250$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 251CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 252CFG_SCMI_MSG_SHM_MSG ?= y 253CFG_SCMI_MSG_SMT ?= y 254endif # !CFG_SCMI_SCPFW 255endif # CFG_SCMI_PTA 256 257CFG_SCMI_SCPFW ?= n 258ifeq ($(CFG_SCMI_SCPFW),y) 259$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1) 260endif 261 262CFG_SCMI_MSG_DRIVERS ?= n 263ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 264$(call force,CFG_SCMI_MSG_CLOCK,y) 265$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 266CFG_SCMI_MSG_SHM_MSG ?= y 267CFG_SCMI_MSG_SMT ?= y 268CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 269$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 270endif 271 272ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 273CFG_HWRNG_PTA ?= y 274endif 275ifeq ($(CFG_HWRNG_PTA),y) 276$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 277$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 278$(call force,CFG_HWRNG_QUALITY,1024) 279endif 280 281# Provision enough threads to pass xtest 282ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 283ifeq ($(CFG_WITH_PAGER),y) 284CFG_NUM_THREADS ?= 3 285else 286CFG_NUM_THREADS ?= 10 287endif 288endif 289 290# Default enable some test facitilites 291CFG_ENABLE_EMBEDDED_TESTS ?= y 292CFG_WITH_STATS ?= y 293 294# Enable OTP update with BSEC driver 295CFG_STM32_BSEC_WRITE ?= y 296 297# Default disable some support for pager memory size constraint 298ifeq ($(CFG_WITH_PAGER),y) 299CFG_TEE_CORE_DEBUG ?= n 300CFG_UNWIND ?= n 301CFG_LOCKDEP ?= n 302CFG_TA_BGET_TEST ?= n 303# Default disable early TA compression to support a smaller HEAP size 304CFG_EARLY_TA_COMPRESS ?= n 305CFG_CORE_HEAP_SIZE ?= 49152 306endif 307 308# Non-secure UART and GPIO/pinctrl for the output console 309CFG_WITH_NSEC_GPIOS ?= y 310CFG_WITH_NSEC_UARTS ?= y 311# UART instance used for early console (0 disables early console) 312CFG_STM32_EARLY_CONSOLE_UART ?= 4 313 314# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 315# Disable the HUK by default as it requires a product specific configuration. 316# 317# Configuration must provide OTP indices where HUK is loaded. 318# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 319# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 320# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 321# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 322# 323# Configuration must provide the HUK generation scheme. The following switches 324# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 325# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 326# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 327# content derived with the device UID fuses content. See derivation scheme 328# in stm32mp15_huk.c implementation. 329CFG_STM32MP15_HUK ?= n 330CFG_STM32_HUK_FROM_DT ?= n 331 332ifeq ($(CFG_STM32MP15_HUK),y) 333ifneq ($(CFG_STM32_HUK_FROM_DT),y) 334ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 335$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 336$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 337$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 338$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 339endif 340ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 341$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 342endif 343ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 344$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 345endif 346ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 347$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 348endif 349ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 350$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 351endif 352endif # CFG_STM32_HUK_FROM_DT 353 354CFG_STM32MP15_HUK_BSEC_KEY ?= y 355CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 356ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 357$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 358else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 359$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 360endif 361endif # CFG_STM32MP15_HUK 362 363CFG_TEE_CORE_DEBUG ?= y 364CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 365 366# Sanity on choice config switches 367ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 368$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 369endif 370