1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 3flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 4flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 5flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 6 7flavor_dts_file-135F_DK = stm32mp135f-dk.dts 8 9flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 10 $(flavor_dts_file-135F_DK) 11 12flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 13 14flavorlist-cryp-1G = $(flavor_dts_file-157C_ED1) \ 15 $(flavor_dts_file-157C_EV1) 16 17flavorlist-no_cryp = $(flavorlist-no_cryp-512M) 18 19flavorlist-512M = $(flavorlist-cryp-512M) \ 20 $(flavorlist-no_cryp-512M) 21 22flavorlist-1G = $(flavorlist-cryp-1G) 23 24flavorlist-MP15 = $(flavor_dts_file-157A_DK1) \ 25 $(flavor_dts_file-157C_DK2) \ 26 $(flavor_dts_file-157C_ED1) \ 27 $(flavor_dts_file-157C_EV1) 28 29flavorlist-MP13 = $(flavor_dts_file-135F_DK) 30 31ifneq ($(PLATFORM_FLAVOR),) 32ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 33$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 34endif 35CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 36endif 37 38ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 39$(call force,CFG_STM32_CRYP,n) 40endif 41 42ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 43$(call force,CFG_STM32MP13,y) 44endif 45 46ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 47$(call force,CFG_STM32MP15,y) 48endif 49 50# CFG_STM32MP1x switches are exclusive. 51# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 52# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 53ifeq ($(CFG_STM32MP13),y) 54$(call force,CFG_STM32MP15,n) 55else 56$(call force,CFG_STM32MP15,y) 57$(call force,CFG_STM32MP13,n) 58endif 59ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 60$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 61endif 62ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 63$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 64endif 65 66include core/arch/arm/cpu/cortex-a7.mk 67 68$(call force,CFG_DRIVERS_CLK,y) 69$(call force,CFG_GIC,y) 70$(call force,CFG_INIT_CNTVOFF,y) 71$(call force,CFG_PSCI_ARM32,y) 72$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 73$(call force,CFG_SM_PLATFORM_HANDLER,y) 74$(call force,CFG_STM32_SHARED_IO,y) 75 76ifeq ($(CFG_STM32MP13),y) 77$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 78$(call force,CFG_CORE_RESERVED_SHM,n) 79$(call force,CFG_DRIVERS_CLK_FIXED,y) 80$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 81$(call force,CFG_STM32_GPIO,y) 82$(call force,CFG_STM32_RNG,n) 83$(call force,CFG_STM32MP_CLK_CORE,y) 84$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 85$(call force,CFG_STM32MP13_CLK,y) 86$(call force,CFG_TEE_CORE_NB_CORE,1) 87$(call force,CFG_WITH_NSEC_GPIOS,n) 88CFG_STM32MP_OPP_COUNT ?= 2 89CFG_WITH_PAGER ?= n 90endif # CFG_STM32MP13 91 92ifeq ($(CFG_STM32MP15),y) 93$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 94$(call force,CFG_DRIVERS_CLK_FIXED,n) 95$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 96$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 97$(call force,CFG_STM32MP15_CLK,y) 98CFG_CORE_RESERVED_SHM ?= y 99CFG_TEE_CORE_NB_CORE ?= 2 100CFG_WITH_PAGER ?= y 101endif # CFG_STM32MP15 102 103CFG_WITH_LPAE ?= y 104CFG_WITH_SOFTWARE_PRNG ?= y 105CFG_MMAP_REGIONS ?= 23 106CFG_DTB_MAX_SIZE ?= (256 * 1024) 107CFG_CORE_ASLR ?= n 108 109ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),) 110# Some drivers mandate DT support 111$(call force,CFG_DRIVERS_CLK_DT,n) 112$(call force,CFG_STM32_CRYP,n) 113$(call force,CFG_STM32_GPIO,n) 114$(call force,CFG_STM32_I2C,n) 115$(call force,CFG_STM32_IWDG,n) 116$(call force,CFG_STM32_TAMP,n) 117$(call force,CFG_STPMIC1,n) 118$(call force,CFG_STM32MP1_SCMI_SIP,n) 119$(call force,CFG_SCMI_PTA,n) 120else 121$(call force,CFG_DRIVERS_CLK_DT,y) 122endif 123 124ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 125CFG_TZDRAM_START ?= 0xde000000 126CFG_DRAM_SIZE ?= 0x20000000 127endif 128 129CFG_DRAM_BASE ?= 0xc0000000 130CFG_DRAM_SIZE ?= 0x40000000 131CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 132CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 133ifeq ($(CFG_STM32MP15),y) 134CFG_TZDRAM_START ?= 0xfe000000 135CFG_TZDRAM_SIZE ?= 0x01e00000 136CFG_TZSRAM_START ?= 0x2ffc0000 137CFG_TZSRAM_SIZE ?= 0x0003f000 138ifeq ($(CFG_CORE_RESERVED_SHM),y) 139CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 140CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 141endif 142else 143CFG_TZDRAM_SIZE ?= 0x02000000 144CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 145endif #CFG_STM32MP15 146 147CFG_STM32_BSEC ?= y 148CFG_STM32_CRYP ?= y 149CFG_STM32_ETZPC ?= y 150CFG_STM32_GPIO ?= y 151CFG_STM32_I2C ?= y 152CFG_STM32_IWDG ?= y 153CFG_STM32_RNG ?= y 154CFG_STM32_RSTCTRL ?= y 155CFG_STM32_TAMP ?= y 156CFG_STM32_UART ?= y 157CFG_STPMIC1 ?= y 158CFG_TZC400 ?= y 159 160ifeq ($(CFG_STPMIC1),y) 161$(call force,CFG_STM32_I2C,y) 162$(call force,CFG_STM32_GPIO,y) 163endif 164 165# if any crypto driver is enabled, enable the crypto-framework layer 166ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y) 167$(call force,CFG_STM32_CRYPTO_DRIVER,y) 168endif 169 170CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 171$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 172 173CFG_WDT ?= $(CFG_STM32_IWDG) 174 175# Platform specific configuration 176CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 177 178# SiP/OEM service for non-secure world 179CFG_STM32_BSEC_SIP ?= y 180CFG_STM32MP1_SCMI_SIP ?= n 181ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 182$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 183$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 184$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 185endif 186 187# Default enable SCMI PTA support 188CFG_SCMI_PTA ?= y 189ifeq ($(CFG_SCMI_PTA),y) 190$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 191$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 192CFG_SCMI_MSG_SHM_MSG ?= y 193CFG_SCMI_MSG_SMT ?= y 194endif 195 196CFG_SCMI_MSG_DRIVERS ?= n 197ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 198$(call force,CFG_SCMI_MSG_CLOCK,y) 199$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 200CFG_SCMI_MSG_SHM_MSG ?= y 201CFG_SCMI_MSG_SMT ?= y 202CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 203$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 204endif 205 206ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 207CFG_HWRNG_PTA ?= y 208endif 209ifeq ($(CFG_HWRNG_PTA),y) 210$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 211$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 212$(call force,CFG_HWRNG_QUALITY,1024) 213endif 214 215# Provision enough threads to pass xtest 216ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 217ifeq ($(CFG_WITH_PAGER),y) 218CFG_NUM_THREADS ?= 3 219else 220CFG_NUM_THREADS ?= 10 221endif 222endif 223 224# Default enable some test facitilites 225CFG_ENABLE_EMBEDDED_TESTS ?= y 226CFG_WITH_STATS ?= y 227 228# Enable to allow debug 229CFG_STM32_BSEC_WRITE ?= $(CFG_TEE_CORE_DEBUG) 230 231# Default disable some support for pager memory size constraint 232ifeq ($(CFG_WITH_PAGER),y) 233CFG_TEE_CORE_DEBUG ?= n 234CFG_UNWIND ?= n 235CFG_LOCKDEP ?= n 236CFG_TA_BGET_TEST ?= n 237# Default disable early TA compression to support a smaller HEAP size 238CFG_EARLY_TA_COMPRESS ?= n 239CFG_CORE_HEAP_SIZE ?= 49152 240endif 241 242# Non-secure UART and GPIO/pinctrl for the output console 243CFG_WITH_NSEC_GPIOS ?= y 244CFG_WITH_NSEC_UARTS ?= y 245# UART instance used for early console (0 disables early console) 246CFG_STM32_EARLY_CONSOLE_UART ?= 4 247 248# Sanity on choice config switches 249ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 250$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 251endif 252