1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8 9flavor_dts_file-135F_DK = stm32mp135f-dk.dts 10 11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 12 $(flavor_dts_file-135F_DK) 13 14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 15 16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 17 $(flavor_dts_file-157C_ED1) \ 18 $(flavor_dts_file-157C_EV1) 19 20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 21 22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 23 $(flavorlist-no_cryp-1G) 24 25flavorlist-512M = $(flavorlist-cryp-512M) \ 26 $(flavorlist-no_cryp-512M) 27 28flavorlist-1G = $(flavorlist-cryp-1G) \ 29 $(flavorlist-no_cryp-1G) 30 31flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 32 $(flavor_dts_file-157C_DK2) \ 33 $(flavor_dts_file-157C_ED1) \ 34 $(flavor_dts_file-157C_EV1) 35 36flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 37 $(flavor_dts_file-157A_DK1) \ 38 $(flavor_dts_file-157C_DHCOM_PDK2) \ 39 $(flavor_dts_file-157C_DK2) \ 40 $(flavor_dts_file-157C_ED1) \ 41 $(flavor_dts_file-157C_EV1) 42 43flavorlist-MP13 = $(flavor_dts_file-135F_DK) 44 45ifneq ($(PLATFORM_FLAVOR),) 46ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 47$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 48endif 49CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 50endif 51CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 52 53ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 54$(call force,CFG_STM32_CRYP,n) 55$(call force,CFG_STM32_SAES,n) 56endif 57 58ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 59$(call force,CFG_HWRNG_PTA,n) 60$(call force,CFG_WITH_SOFTWARE_PRNG,y) 61endif 62 63ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 64CFG_STM32MP15_HUK ?= y 65CFG_STM32_HUK_FROM_DT ?= y 66endif 67 68ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 69$(call force,CFG_STM32MP13,y) 70endif 71 72ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 73$(call force,CFG_STM32MP15,y) 74endif 75 76# CFG_STM32MP1x switches are exclusive. 77# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 78# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 79ifeq ($(CFG_STM32MP13),y) 80$(call force,CFG_STM32MP15,n) 81else 82$(call force,CFG_STM32MP15,y) 83$(call force,CFG_STM32MP13,n) 84endif 85ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 86$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 87endif 88ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 89$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 90endif 91 92include core/arch/arm/cpu/cortex-a7.mk 93 94$(call force,CFG_DRIVERS_CLK,y) 95$(call force,CFG_DRIVERS_CLK_DT,y) 96$(call force,CFG_DRIVERS_GPIO,y) 97$(call force,CFG_DRIVERS_PINCTRL,y) 98$(call force,CFG_DRIVERS_REGULATOR,y) 99$(call force,CFG_GIC,y) 100$(call force,CFG_INIT_CNTVOFF,y) 101$(call force,CFG_PSCI_ARM32,y) 102$(call force,CFG_REGULATOR_FIXED,y) 103$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 104$(call force,CFG_SM_PLATFORM_HANDLER,y) 105$(call force,CFG_STM32_SHARED_IO,y) 106 107ifeq ($(CFG_STM32MP13),y) 108$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 109$(call force,CFG_CORE_ASYNC_NOTIF,y) 110$(call force,CFG_CORE_ASYNC_NOTIF_GIC_INTID,31) 111$(call force,CFG_CORE_RESERVED_SHM,n) 112$(call force,CFG_DRIVERS_CLK_FIXED,y) 113$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 114$(call force,CFG_STM32_GPIO,y) 115$(call force,CFG_STM32_VREFBUF,y) 116$(call force,CFG_STM32MP_CLK_CORE,y) 117$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 118$(call force,CFG_STM32MP13_CLK,y) 119$(call force,CFG_STM32MP13_REGULATOR_IOD,y) 120$(call force,CFG_TEE_CORE_NB_CORE,1) 121$(call force,CFG_WITH_NSEC_GPIOS,n) 122CFG_EXTERNAL_DT ?= n 123CFG_STM32MP_OPP_COUNT ?= 2 124CFG_WITH_PAGER ?= n 125endif # CFG_STM32MP13 126 127ifeq ($(CFG_STM32MP15),y) 128$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 129$(call force,CFG_DRIVERS_CLK_FIXED,n) 130$(call force,CFG_HALT_CORES_ON_PANIC_SGI,15) 131$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 132$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 133$(call force,CFG_STM32_SAES,n) 134$(call force,CFG_STM32MP15_CLK,y) 135CFG_CORE_RESERVED_SHM ?= n 136CFG_HALT_CORES_ON_PANIC ?= y 137CFG_EXTERNAL_DT ?= y 138CFG_STM32_BSEC_SIP ?= y 139CFG_TEE_CORE_NB_CORE ?= 2 140CFG_WITH_PAGER ?= y 141CFG_WITH_SOFTWARE_PRNG ?= y 142endif # CFG_STM32MP15 143 144ifeq ($(CFG_WITH_PAGER),y) 145CFG_WITH_LPAE ?= n 146endif 147CFG_WITH_LPAE ?= y 148CFG_MMAP_REGIONS ?= 23 149CFG_DTB_MAX_SIZE ?= (256 * 1024) 150CFG_CORE_ASLR ?= n 151 152ifneq ($(CFG_WITH_LPAE),y) 153# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 154CFG_TEE_RAM_VA_SIZE ?= 0x00200000 155endif 156 157ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 158CFG_TZDRAM_START ?= 0xde000000 159CFG_DRAM_SIZE ?= 0x20000000 160endif 161 162CFG_DRAM_BASE ?= 0xc0000000 163CFG_DRAM_SIZE ?= 0x40000000 164 165# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 166# device memory mapped SRAM used for SCMI message transfers. 167# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 168# native shared memory for SCMI communication instead of SRAM. 169# 170# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 171# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 172# disabled. 173CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 174ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 175$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 176else 177CFG_STM32MP1_SCMI_SHM_BASE ?= 0 178endif 179$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 180 181ifeq ($(CFG_STM32MP15),y) 182CFG_TZDRAM_START ?= 0xfe000000 183ifeq ($(CFG_CORE_RESERVED_SHM),y) 184CFG_TZDRAM_SIZE ?= 0x01e00000 185else 186CFG_TZDRAM_SIZE ?= 0x02000000 187endif 188CFG_TZSRAM_START ?= 0x2ffc0000 189CFG_TZSRAM_SIZE ?= 0x0003f000 190ifeq ($(CFG_CORE_RESERVED_SHM),y) 191CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 192CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 193endif 194else 195CFG_TZDRAM_SIZE ?= 0x02000000 196CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 197endif #CFG_STM32MP15 198 199CFG_STM32_BSEC ?= y 200CFG_STM32_CRYP ?= y 201CFG_STM32_ETZPC ?= y 202CFG_STM32_GPIO ?= y 203CFG_STM32_I2C ?= y 204CFG_STM32_IWDG ?= y 205CFG_STM32_RNG ?= y 206CFG_STM32_RSTCTRL ?= y 207CFG_STM32_SAES ?= y 208CFG_STM32_TAMP ?= y 209CFG_STM32_UART ?= y 210CFG_STPMIC1 ?= y 211CFG_TZC400 ?= y 212 213CFG_DRIVERS_I2C ?= $(CFG_STM32_I2C) 214CFG_REGULATOR_GPIO ?= $(CFG_STM32_GPIO) 215 216CFG_WITH_SOFTWARE_PRNG ?= n 217ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 218$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 219endif 220 221ifeq ($(CFG_STPMIC1),y) 222$(call force,CFG_STM32_I2C,y) 223$(call force,CFG_STM32_GPIO,y) 224endif 225 226# If any crypto driver is enabled, enable the crypto-framework layer 227ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y) 228$(call force,CFG_STM32_CRYPTO_DRIVER,y) 229endif 230 231CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 232$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 233 234CFG_WDT ?= $(CFG_STM32_IWDG) 235 236# Platform specific configuration 237CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 238 239# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 240ifneq ($(CFG_SCMI_SCPFW),y) 241CFG_SCMI_MSG_DRIVERS ?= y 242endif 243 244# SiP/OEM service for non-secure world 245CFG_STM32_BSEC_SIP ?= n 246CFG_STM32MP1_SCMI_SIP ?= n 247ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 248$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 249$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 250$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 251endif 252 253# Enable BSEC PTA for fuses access management 254CFG_STM32_BSEC_PTA ?= y 255ifeq ($(CFG_STM32_BSEC_PTA),y) 256$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 257endif 258 259# Default enable SCMI PTA support 260CFG_SCMI_PTA ?= y 261ifeq ($(CFG_SCMI_PTA),y) 262ifneq ($(CFG_SCMI_SCPFW),y) 263$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 264CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 265CFG_SCMI_MSG_SHM_MSG ?= y 266CFG_SCMI_MSG_SMT ?= y 267endif # !CFG_SCMI_SCPFW 268endif # CFG_SCMI_PTA 269 270CFG_SCMI_SCPFW ?= n 271ifeq ($(CFG_SCMI_SCPFW),y) 272$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1) 273endif 274 275CFG_SCMI_MSG_DRIVERS ?= n 276ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 277$(call force,CFG_SCMI_MSG_CLOCK,y) 278$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 279CFG_SCMI_MSG_SHM_MSG ?= y 280CFG_SCMI_MSG_SMT ?= y 281CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 282$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 283endif 284 285ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 286CFG_HWRNG_PTA ?= y 287endif 288ifeq ($(CFG_HWRNG_PTA),y) 289$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 290$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 291$(call force,CFG_HWRNG_QUALITY,1024) 292endif 293 294# Provision enough threads to pass xtest 295ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 296ifeq ($(CFG_WITH_PAGER),y) 297CFG_NUM_THREADS ?= 3 298else 299CFG_NUM_THREADS ?= 10 300endif 301endif 302 303# Default enable some test facitilites 304CFG_ENABLE_EMBEDDED_TESTS ?= y 305CFG_WITH_STATS ?= y 306 307# Enable OTP update with BSEC driver 308CFG_STM32_BSEC_WRITE ?= y 309 310# Default disable some support for pager memory size constraint 311ifeq ($(CFG_WITH_PAGER),y) 312CFG_TEE_CORE_DEBUG ?= n 313CFG_UNWIND ?= n 314CFG_LOCKDEP ?= n 315CFG_TA_BGET_TEST ?= n 316# Default disable early TA compression to support a smaller HEAP size 317CFG_EARLY_TA_COMPRESS ?= n 318CFG_CORE_HEAP_SIZE ?= 49152 319endif 320 321# Non-secure UART and GPIO/pinctrl for the output console 322CFG_WITH_NSEC_GPIOS ?= y 323CFG_WITH_NSEC_UARTS ?= y 324# UART instance used for early console (0 disables early console) 325CFG_STM32_EARLY_CONSOLE_UART ?= 4 326 327# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 328# Disable the HUK by default as it requires a product specific configuration. 329# 330# Configuration must provide OTP indices where HUK is loaded. 331# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 332# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 333# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 334# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 335# 336# Configuration must provide the HUK generation scheme. The following switches 337# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 338# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 339# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 340# content derived with the device UID fuses content. See derivation scheme 341# in stm32mp15_huk.c implementation. 342CFG_STM32MP15_HUK ?= n 343CFG_STM32_HUK_FROM_DT ?= n 344 345ifeq ($(CFG_STM32MP15_HUK),y) 346ifneq ($(CFG_STM32_HUK_FROM_DT),y) 347ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 348$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 349$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 350$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 351$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 352endif 353ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 354$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 355endif 356ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 357$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 358endif 359ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 360$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 361endif 362ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 363$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 364endif 365endif # CFG_STM32_HUK_FROM_DT 366 367CFG_STM32MP15_HUK_BSEC_KEY ?= y 368CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 369ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 370$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 371else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 372$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 373endif 374endif # CFG_STM32MP15_HUK 375 376CFG_TEE_CORE_DEBUG ?= y 377CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 378 379# Sanity on choice config switches 380ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 381$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 382endif 383