1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8flavor_dts_file-157A_DK1_SCMI = stm32mp157a-dk1-scmi.dts 9flavor_dts_file-157C_DK2_SCMI = stm32mp157c-dk2-scmi.dts 10flavor_dts_file-157C_ED1_SCMI = stm32mp157c-ed1-scmi.dts 11flavor_dts_file-157C_EV1_SCMI = stm32mp157c-ev1-scmi.dts 12 13flavor_dts_file-135F_DK = stm32mp135f-dk.dts 14 15flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 16 $(flavor_dts_file-157C_DK2_SCMI) \ 17 $(flavor_dts_file-135F_DK) 18 19flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) \ 20 $(flavor_dts_file-157A_DK1_SCMI) 21 22flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 23 $(flavor_dts_file-157C_ED1) \ 24 $(flavor_dts_file-157C_EV1) \ 25 $(flavor_dts_file-157C_ED1_SCMI) \ 26 $(flavor_dts_file-157C_EV1_SCMI) 27 28flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 29 30flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 31 $(flavorlist-no_cryp-1G) 32 33flavorlist-512M = $(flavorlist-cryp-512M) \ 34 $(flavorlist-no_cryp-512M) 35 36flavorlist-1G = $(flavorlist-cryp-1G) \ 37 $(flavorlist-no_cryp-1G) 38 39flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 40 $(flavor_dts_file-157C_DK2) \ 41 $(flavor_dts_file-157C_ED1) \ 42 $(flavor_dts_file-157C_EV1) \ 43 $(flavor_dts_file-157A_DK1_SCMI) \ 44 $(flavor_dts_file-157C_DK2_SCMI) \ 45 $(flavor_dts_file-157C_ED1_SCMI) \ 46 $(flavor_dts_file-157C_EV1_SCMI) 47 48flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 49 $(flavor_dts_file-157A_DK1) \ 50 $(flavor_dts_file-157C_DHCOM_PDK2) \ 51 $(flavor_dts_file-157C_DK2) \ 52 $(flavor_dts_file-157C_ED1) \ 53 $(flavor_dts_file-157C_EV1) \ 54 $(flavor_dts_file-157A_DK1_SCMI) \ 55 $(flavor_dts_file-157C_DK2_SCMI) \ 56 $(flavor_dts_file-157C_ED1_SCMI) \ 57 $(flavor_dts_file-157C_EV1_SCMI) 58 59flavorlist-MP13 = $(flavor_dts_file-135F_DK) 60 61ifneq ($(PLATFORM_FLAVOR),) 62ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 63$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 64endif 65CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 66endif 67CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 68 69ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 70$(call force,CFG_STM32_CRYP,n) 71$(call force,CFG_STM32_SAES,n) 72endif 73 74ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 75$(call force,CFG_HWRNG_PTA,n) 76$(call force,CFG_WITH_SOFTWARE_PRNG,y) 77endif 78 79ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 80CFG_STM32MP15_HUK ?= y 81CFG_STM32_HUK_FROM_DT ?= y 82endif 83 84ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 85$(call force,CFG_STM32MP13,y) 86endif 87 88ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 89$(call force,CFG_STM32MP15,y) 90endif 91 92# CFG_STM32MP1x switches are exclusive. 93# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 94# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 95ifeq ($(CFG_STM32MP13),y) 96$(call force,CFG_STM32MP15,n) 97else 98$(call force,CFG_STM32MP15,y) 99$(call force,CFG_STM32MP13,n) 100endif 101ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 102$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 103endif 104ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 105$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 106endif 107 108include core/arch/arm/cpu/cortex-a7.mk 109 110$(call force,CFG_DRIVERS_CLK,y) 111$(call force,CFG_DRIVERS_CLK_DT,y) 112$(call force,CFG_DRIVERS_GPIO,y) 113$(call force,CFG_DRIVERS_PINCTRL,y) 114$(call force,CFG_DRIVERS_REGULATOR,y) 115$(call force,CFG_GIC,y) 116$(call force,CFG_INIT_CNTVOFF,y) 117$(call force,CFG_PSCI_ARM32,y) 118$(call force,CFG_REGULATOR_FIXED,y) 119$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 120$(call force,CFG_SM_PLATFORM_HANDLER,y) 121$(call force,CFG_STM32_SHARED_IO,y) 122 123ifeq ($(CFG_STM32MP13),y) 124$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 125$(call force,CFG_CORE_ASYNC_NOTIF,y) 126$(call force,CFG_CORE_ASYNC_NOTIF_GIC_INTID,31) 127$(call force,CFG_CORE_RESERVED_SHM,n) 128$(call force,CFG_DRIVERS_CLK_FIXED,y) 129$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 130$(call force,CFG_STM32_GPIO,y) 131$(call force,CFG_STM32_VREFBUF,y) 132$(call force,CFG_STM32MP_CLK_CORE,y) 133$(call force,CFG_STM32MP1_SHARED_RESOURCES,n) 134$(call force,CFG_STM32MP1_RSTCTRL,y) 135$(call force,CFG_STM32MP13_CLK,y) 136$(call force,CFG_STM32MP13_REGULATOR_IOD,y) 137$(call force,CFG_TEE_CORE_NB_CORE,1) 138$(call force,CFG_WITH_NSEC_GPIOS,n) 139CFG_EXTERNAL_DT ?= n 140CFG_STM32MP_OPP_COUNT ?= 2 141CFG_WITH_PAGER ?= n 142endif # CFG_STM32MP13 143 144ifeq ($(CFG_STM32MP15),y) 145$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 146$(call force,CFG_DRIVERS_CLK_FIXED,n) 147$(call force,CFG_HALT_CORES_ON_PANIC_SGI,15) 148$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 149$(call force,CFG_STM32MP1_SHARED_RESOURCES,y) 150$(call force,CFG_STM32_SAES,n) 151$(call force,CFG_STM32MP1_RSTCTRL,y) 152$(call force,CFG_STM32MP15_CLK,y) 153CFG_CORE_RESERVED_SHM ?= n 154CFG_HALT_CORES_ON_PANIC ?= y 155CFG_EXTERNAL_DT ?= y 156CFG_STM32_BSEC_SIP ?= y 157CFG_TEE_CORE_NB_CORE ?= 2 158CFG_WITH_PAGER ?= y 159CFG_WITH_SOFTWARE_PRNG ?= y 160endif # CFG_STM32MP15 161 162ifeq ($(CFG_WITH_PAGER),y) 163CFG_WITH_LPAE ?= n 164endif 165CFG_WITH_LPAE ?= y 166CFG_MMAP_REGIONS ?= 23 167CFG_DTB_MAX_SIZE ?= (256 * 1024) 168CFG_CORE_ASLR ?= n 169 170CFG_STM32MP_REMOTEPROC ?= n 171CFG_DRIVERS_REMOTEPROC ?= $(CFG_STM32MP_REMOTEPROC) 172CFG_REMOTEPROC_PTA ?= $(CFG_STM32MP_REMOTEPROC) 173ifeq ($(CFG_REMOTEPROC_PTA),y) 174# Remoteproc early TA for coprocessor firmware management in boot stages 175CFG_IN_TREE_EARLY_TAS += remoteproc/80a4c275-0a47-4905-8285-1486a9771a08 176# Embed public part of this key in OP-TEE OS 177RPROC_SIGN_KEY ?= keys/default.pem 178endif 179 180ifneq ($(CFG_WITH_LPAE),y) 181# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 182CFG_TEE_RAM_VA_SIZE ?= 0x00200000 183endif 184 185ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 186CFG_TZDRAM_START ?= 0xde000000 187CFG_DRAM_SIZE ?= 0x20000000 188endif 189 190CFG_DRAM_BASE ?= 0xc0000000 191CFG_DRAM_SIZE ?= 0x40000000 192 193# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 194# device memory mapped SRAM used for SCMI message transfers. 195# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 196# native shared memory for SCMI communication instead of SRAM. 197# 198# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 199# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 200# disabled. 201CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 202ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 203$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 204CFG_TZSRAM_SIZE ?= 0x0003f000 205else 206CFG_STM32MP1_SCMI_SHM_BASE ?= 0 207endif 208$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 209 210ifeq ($(CFG_STM32MP15),y) 211CFG_TZDRAM_START ?= 0xfe000000 212ifeq ($(CFG_CORE_RESERVED_SHM),y) 213CFG_TZDRAM_SIZE ?= 0x01e00000 214else 215CFG_TZDRAM_SIZE ?= 0x02000000 216endif 217CFG_TZSRAM_START ?= 0x2ffc0000 218CFG_TZSRAM_SIZE ?= 0x00040000 219ifeq ($(CFG_CORE_RESERVED_SHM),y) 220CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 221CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 222endif 223else 224CFG_TZDRAM_SIZE ?= 0x02000000 225CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 226endif #CFG_STM32MP15 227 228CFG_STM32_BSEC ?= y 229CFG_STM32_CRYP ?= y 230CFG_STM32_ETZPC ?= y 231CFG_STM32_GPIO ?= y 232CFG_STM32_I2C ?= y 233CFG_STM32_IWDG ?= y 234CFG_STM32_RNG ?= y 235CFG_STM32_RSTCTRL ?= y 236CFG_STM32_SAES ?= y 237CFG_STM32_TAMP ?= y 238CFG_STM32_UART ?= y 239CFG_STPMIC1 ?= y 240CFG_TZC400 ?= y 241 242CFG_DRIVERS_I2C ?= $(CFG_STM32_I2C) 243CFG_REGULATOR_GPIO ?= $(CFG_STM32_GPIO) 244 245CFG_WITH_SOFTWARE_PRNG ?= n 246ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 247$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 248endif 249 250ifeq ($(CFG_STPMIC1),y) 251$(call force,CFG_STM32_I2C,y) 252$(call force,CFG_STM32_GPIO,y) 253endif 254 255# If any crypto driver is enabled, enable the crypto-framework layer 256ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP CFG_STM32_SAES),y) 257$(call force,CFG_STM32_CRYPTO_DRIVER,y) 258endif 259 260CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 261$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 262 263CFG_WDT ?= $(CFG_STM32_IWDG) 264CFG_WDT_SM_HANDLER ?= $(CFG_WDT) 265CFG_WDT_SM_HANDLER_ID ?= 0xbc000000 266 267# Platform specific configuration 268CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 269 270# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 271ifneq ($(CFG_SCMI_SCPFW),y) 272CFG_SCMI_MSG_DRIVERS ?= y 273endif 274 275# SiP/OEM service for non-secure world 276CFG_STM32_BSEC_SIP ?= n 277CFG_STM32MP1_SCMI_SIP ?= n 278ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 279$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 280$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 281$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 282endif 283 284# Enable BSEC PTA for fuses access management 285CFG_STM32_BSEC_PTA ?= y 286ifeq ($(CFG_STM32_BSEC_PTA),y) 287$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 288endif 289 290# Default enable SCMI PTA support 291CFG_SCMI_PTA ?= y 292ifeq ($(CFG_SCMI_PTA),y) 293ifneq ($(CFG_SCMI_SCPFW),y) 294$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 295CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 296CFG_SCMI_MSG_SHM_MSG ?= y 297CFG_SCMI_MSG_SMT ?= y 298endif # !CFG_SCMI_SCPFW 299endif # CFG_SCMI_PTA 300 301CFG_SCMI_SCPFW ?= n 302ifeq ($(CFG_SCMI_SCPFW),y) 303$(call force,CFG_SCMI_SCPFW_PRODUCT,stm32mp1) 304endif 305 306CFG_SCMI_MSG_DRIVERS ?= n 307ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 308$(call force,CFG_SCMI_MSG_CLOCK,y) 309$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 310CFG_SCMI_MSG_SHM_MSG ?= y 311CFG_SCMI_MSG_SMT ?= y 312CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 313$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 314endif 315 316ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 317CFG_HWRNG_PTA ?= y 318endif 319ifeq ($(CFG_HWRNG_PTA),y) 320$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 321$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 322$(call force,CFG_HWRNG_QUALITY,1024) 323endif 324 325# Provision enough threads to pass xtest 326ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 327ifeq ($(CFG_WITH_PAGER),y) 328CFG_NUM_THREADS ?= 3 329else 330CFG_NUM_THREADS ?= 10 331endif 332endif 333 334# Default enable some test facitilites 335CFG_ENABLE_EMBEDDED_TESTS ?= y 336CFG_WITH_STATS ?= y 337 338# Default enable software fallback on crypto drivers 339CFG_STM32_SAES_SW_FALLBACK ?= y 340 341# Enable OTP update with BSEC driver 342CFG_STM32_BSEC_WRITE ?= y 343 344# Default disable some support for pager memory size constraint 345ifeq ($(CFG_WITH_PAGER),y) 346CFG_TEE_CORE_DEBUG ?= n 347CFG_UNWIND ?= n 348CFG_LOCKDEP ?= n 349CFG_TA_BGET_TEST ?= n 350endif 351 352# Non-secure UART and GPIO/pinctrl for the output console 353CFG_WITH_NSEC_GPIOS ?= y 354CFG_WITH_NSEC_UARTS ?= y 355# UART instance used for early console (0 disables early console) 356CFG_STM32_EARLY_CONSOLE_UART ?= 4 357 358# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 359# Disable the HUK by default as it requires a product specific configuration. 360# 361# Configuration must provide OTP indices where HUK is loaded. 362# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 363# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 364# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 365# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 366# 367# Configuration must provide the HUK generation scheme. The following switches 368# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 369# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 370# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 371# content derived with the device UID fuses content. See derivation scheme 372# in stm32mp15_huk.c implementation. 373CFG_STM32MP15_HUK ?= n 374CFG_STM32_HUK_FROM_DT ?= n 375 376ifeq ($(CFG_STM32MP15_HUK),y) 377ifneq ($(CFG_STM32_HUK_FROM_DT),y) 378ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 379$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 380$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 381$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 382$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 383endif 384ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 385$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 386endif 387ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 388$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 389endif 390ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 391$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 392endif 393ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 394$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 395endif 396endif # CFG_STM32_HUK_FROM_DT 397 398CFG_STM32MP15_HUK_BSEC_KEY ?= y 399CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 400ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 401$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 402else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 403$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 404endif 405endif # CFG_STM32MP15_HUK 406 407CFG_TEE_CORE_DEBUG ?= y 408CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 409 410# Sanity on choice config switches 411ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 412$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 413endif 414