xref: /optee_os/core/arch/arm/plat-stm32mp1/conf.mk (revision 088116c9c21911f98b1a9ef9bc2f5e16ee59a4ce) 
1# 1GB and 512MB DDR targets do not locate secure DDR at the same place.
2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts
3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts
4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts
5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts
6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts
7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts
8
9flavor_dts_file-135F_DK = stm32mp135f-dk.dts
10
11flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \
12		       $(flavor_dts_file-135F_DK)
13
14flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1)
15
16flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \
17		     $(flavor_dts_file-157C_ED1) \
18		     $(flavor_dts_file-157C_EV1)
19
20flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96)
21
22flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \
23		  $(flavorlist-no_cryp-1G)
24
25flavorlist-512M = $(flavorlist-cryp-512M) \
26		  $(flavorlist-no_cryp-512M)
27
28flavorlist-1G = $(flavorlist-cryp-1G) \
29		  $(flavorlist-no_cryp-1G)
30
31flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \
32		  $(flavor_dts_file-157A_DK1) \
33		  $(flavor_dts_file-157C_DHCOM_PDK2) \
34		  $(flavor_dts_file-157C_DK2) \
35		  $(flavor_dts_file-157C_ED1) \
36		  $(flavor_dts_file-157C_EV1)
37
38flavorlist-MP13 = $(flavor_dts_file-135F_DK)
39
40ifneq ($(PLATFORM_FLAVOR),)
41ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),)
42$(error Invalid platform flavor $(PLATFORM_FLAVOR))
43endif
44CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR))
45endif
46CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts
47
48ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),)
49$(call force,CFG_STM32_CRYP,n)
50endif
51
52ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),)
53$(call force,CFG_HWRNG_PTA,n)
54$(call force,CFG_WITH_SOFTWARE_PRNG,y)
55endif
56
57ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),)
58$(call force,CFG_STM32MP13,y)
59endif
60
61ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),)
62$(call force,CFG_STM32MP15,y)
63endif
64
65# CFG_STM32MP1x switches are exclusive.
66# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default)
67# - CFG_STM32MP13 is enabled for STM32MP13x-* targets
68ifeq ($(CFG_STM32MP13),y)
69$(call force,CFG_STM32MP15,n)
70else
71$(call force,CFG_STM32MP15,y)
72$(call force,CFG_STM32MP13,n)
73endif
74ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n)
75$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled)
76endif
77ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y)
78$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled)
79endif
80
81include core/arch/arm/cpu/cortex-a7.mk
82
83$(call force,CFG_DRIVERS_CLK,y)
84$(call force,CFG_DRIVERS_CLK_DT,y)
85$(call force,CFG_GIC,y)
86$(call force,CFG_INIT_CNTVOFF,y)
87$(call force,CFG_PSCI_ARM32,y)
88$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
89$(call force,CFG_SM_PLATFORM_HANDLER,y)
90$(call force,CFG_STM32_SHARED_IO,y)
91
92ifeq ($(CFG_STM32MP13),y)
93$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
94$(call force,CFG_CORE_RESERVED_SHM,n)
95$(call force,CFG_DRIVERS_CLK_FIXED,y)
96$(call force,CFG_SECONDARY_INIT_CNTFRQ,n)
97$(call force,CFG_STM32_GPIO,y)
98$(call force,CFG_STM32MP_CLK_CORE,y)
99$(call force,CFG_STM32MP1_SHARED_RESOURCES,n)
100$(call force,CFG_STM32MP13_CLK,y)
101$(call force,CFG_TEE_CORE_NB_CORE,1)
102$(call force,CFG_WITH_NSEC_GPIOS,n)
103CFG_EXTERNAL_DT ?= n
104CFG_STM32MP_OPP_COUNT ?= 2
105CFG_WITH_PAGER ?= n
106endif # CFG_STM32MP13
107
108ifeq ($(CFG_STM32MP15),y)
109$(call force,CFG_BOOT_SECONDARY_REQUEST,y)
110$(call force,CFG_DRIVERS_CLK_FIXED,n)
111$(call force,CFG_SECONDARY_INIT_CNTFRQ,y)
112$(call force,CFG_STM32MP1_SHARED_RESOURCES,y)
113$(call force,CFG_STM32MP15_CLK,y)
114CFG_CORE_RESERVED_SHM ?= y
115CFG_EXTERNAL_DT ?= y
116CFG_STM32_BSEC_SIP ?= y
117CFG_TEE_CORE_NB_CORE ?= 2
118CFG_WITH_PAGER ?= y
119CFG_WITH_SOFTWARE_PRNG ?= y
120endif # CFG_STM32MP15
121
122ifeq ($(CFG_WITH_PAGER),y)
123CFG_WITH_LPAE ?= n
124endif
125CFG_WITH_LPAE ?= y
126CFG_MMAP_REGIONS ?= 23
127CFG_DTB_MAX_SIZE ?= (256 * 1024)
128CFG_CORE_ASLR ?= n
129
130ifneq ($(CFG_WITH_LPAE),y)
131# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB.
132CFG_TEE_RAM_VA_SIZE ?= 0x00200000
133endif
134
135ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),)
136CFG_TZDRAM_START ?= 0xde000000
137CFG_DRAM_SIZE    ?= 0x20000000
138endif
139
140CFG_DRAM_BASE    ?= 0xc0000000
141CFG_DRAM_SIZE    ?= 0x40000000
142CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000
143CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000
144ifeq ($(CFG_STM32MP15),y)
145CFG_TZDRAM_START ?= 0xfe000000
146ifeq ($(CFG_CORE_RESERVED_SHM),y)
147CFG_TZDRAM_SIZE  ?= 0x01e00000
148else
149CFG_TZDRAM_SIZE  ?= 0x02000000
150endif
151CFG_TZSRAM_START ?= 0x2ffc0000
152CFG_TZSRAM_SIZE  ?= 0x0003f000
153ifeq ($(CFG_CORE_RESERVED_SHM),y)
154CFG_SHMEM_START  ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
155CFG_SHMEM_SIZE   ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START))
156endif
157else
158CFG_TZDRAM_SIZE  ?= 0x02000000
159CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE))
160endif #CFG_STM32MP15
161
162CFG_STM32_BSEC ?= y
163CFG_STM32_CRYP ?= y
164CFG_STM32_ETZPC ?= y
165CFG_STM32_GPIO ?= y
166CFG_STM32_I2C ?= y
167CFG_STM32_IWDG ?= y
168CFG_STM32_RNG ?= y
169CFG_STM32_RSTCTRL ?= y
170CFG_STM32_TAMP ?= y
171CFG_STM32_UART ?= y
172CFG_STPMIC1 ?= y
173CFG_TZC400 ?= y
174
175CFG_WITH_SOFTWARE_PRNG ?= n
176ifneq ($(CFG_WITH_SOFTWARE_PRNG),y)
177$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n)
178endif
179
180ifeq ($(CFG_STPMIC1),y)
181$(call force,CFG_STM32_I2C,y)
182$(call force,CFG_STM32_GPIO,y)
183endif
184
185# if any crypto driver is enabled, enable the crypto-framework layer
186ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP),y)
187$(call force,CFG_STM32_CRYPTO_DRIVER,y)
188endif
189
190CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL)
191$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL))
192
193CFG_WDT ?= $(CFG_STM32_IWDG)
194
195# Platform specific configuration
196CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y
197
198# Default enable scmi-msg server if SCP-firmware SCMI server is disabled
199ifneq ($(CFG_SCMI_SCPFW),y)
200CFG_SCMI_MSG_DRIVERS ?= y
201endif
202
203# SiP/OEM service for non-secure world
204CFG_STM32_BSEC_SIP ?= n
205CFG_STM32MP1_SCMI_SIP ?= n
206ifeq ($(CFG_STM32MP1_SCMI_SIP),y)
207$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP)
208$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP)
209$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP)
210endif
211
212# Enable BSEC PTA for fuses access management
213CFG_STM32_BSEC_PTA ?= y
214ifeq ($(CFG_STM32_BSEC_PTA),y)
215$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA)
216endif
217
218# Default enable SCMI PTA support
219CFG_SCMI_PTA ?= y
220ifeq ($(CFG_SCMI_PTA),y)
221ifneq ($(CFG_SCMI_SCPFW),y)
222$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA)
223$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA)
224CFG_SCMI_MSG_SHM_MSG ?= y
225CFG_SCMI_MSG_SMT ?= y
226endif # !CFG_SCMI_SCPFW
227endif # CFG_SCMI_PTA
228
229CFG_SCMI_SCPFW ?= n
230ifeq ($(CFG_SCMI_SCPFW),y)
231$(call force,CFG_SCMI_SCPFW_PRODUCT,optee-stm32mp1)
232endif
233
234CFG_SCMI_MSG_DRIVERS ?= n
235ifeq ($(CFG_SCMI_MSG_DRIVERS),y)
236$(call force,CFG_SCMI_MSG_CLOCK,y)
237$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y)
238CFG_SCMI_MSG_SHM_MSG ?= y
239CFG_SCMI_MSG_SMT ?= y
240CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y
241$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y)
242endif
243
244ifneq ($(CFG_WITH_SOFTWARE_PRNG),y)
245CFG_HWRNG_PTA ?= y
246endif
247ifeq ($(CFG_HWRNG_PTA),y)
248$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA)
249$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA)
250$(call force,CFG_HWRNG_QUALITY,1024)
251endif
252
253# Provision enough threads to pass xtest
254ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP)))
255ifeq ($(CFG_WITH_PAGER),y)
256CFG_NUM_THREADS ?= 3
257else
258CFG_NUM_THREADS ?= 10
259endif
260endif
261
262# Default enable some test facitilites
263CFG_ENABLE_EMBEDDED_TESTS ?= y
264CFG_WITH_STATS ?= y
265
266# Enable OTP update with BSEC driver
267CFG_STM32_BSEC_WRITE ?= y
268
269# Default disable some support for pager memory size constraint
270ifeq ($(CFG_WITH_PAGER),y)
271CFG_TEE_CORE_DEBUG ?= n
272CFG_UNWIND ?= n
273CFG_LOCKDEP ?= n
274CFG_TA_BGET_TEST ?= n
275# Default disable early TA compression to support a smaller HEAP size
276CFG_EARLY_TA_COMPRESS ?= n
277CFG_CORE_HEAP_SIZE ?= 49152
278endif
279
280# Non-secure UART and GPIO/pinctrl for the output console
281CFG_WITH_NSEC_GPIOS ?= y
282CFG_WITH_NSEC_UARTS ?= y
283# UART instance used for early console (0 disables early console)
284CFG_STM32_EARLY_CONSOLE_UART ?= 4
285
286# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses.
287# Disable the HUK by default as it requires a product specific configuration.
288#
289# Configuration must provide OTP indices where HUK is loaded.
290# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used,
291# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word.
292#
293# Configuration must provide the HUK generation scheme. The following switches
294# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable.
295# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content.
296# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses
297# content derived with the device UID fuses content. See derivation scheme
298# in stm32mp15_huk.c implementation.
299CFG_STM32MP15_HUK ?= n
300
301ifeq ($(CFG_STM32MP15_HUK),y)
302ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE))
303$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE)
304$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1))
305$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2))
306$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3))
307endif
308ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0))
309$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0)
310endif
311ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1))
312$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1)
313endif
314ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2))
315$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2)
316endif
317ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3))
318$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3)
319endif
320
321CFG_STM32MP15_HUK_BSEC_KEY ?= y
322CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n
323ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID))
324$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)
325else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y)
326$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive)
327endif
328endif # CFG_STM32MP15_HUK
329
330CFG_TEE_CORE_DEBUG ?= y
331CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG)
332
333# Sanity on choice config switches
334ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y)
335$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive)
336endif
337