1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017, Schneider Electric 4 * Copyright (c) 2020, Linaro Limited 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/ns16550.h> 11 #include <kernel/boot.h> 12 #include <kernel/delay.h> 13 #include <kernel/panic.h> 14 #include <mm/core_memprot.h> 15 #include <mm/core_mmu.h> 16 #include <platform_config.h> 17 #include <rzn1_tz.h> 18 19 #define SYSCTRL_PWRCTRL_CM3 (SYSCTRL_BASE + 0x174) 20 #define SYSCTRL_PWRSTAT_CM3 (SYSCTRL_BASE + 0x178) 21 22 #define SYSCTRL_PWRCTRL_CM3_CLKEN_A BIT(0) 23 #define SYSCTRL_PWRCTRL_CM3_RSTN_A BIT(1) 24 #define SYSCTRL_PWRCTRL_CM3_MIREQ_A BIT(2) 25 26 #define SYSCTRL_PWRSTAT_CM3_MIRACK_A BIT(0) 27 28 /* Timeout waiting for Master Idle Request Acknowledge */ 29 #define IDLE_ACK_TIMEOUT_US 1000 30 31 static struct ns16550_data console_data; 32 33 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 34 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE); 35 register_ddr(DRAM_BASE, DRAM_SIZE); 36 37 void console_init(void) 38 { 39 ns16550_init(&console_data, CONSOLE_UART_BASE, IO_WIDTH_U32, 2); 40 register_serial_console(&console_data.chip); 41 } 42 43 void boot_primary_init_intc(void) 44 { 45 gic_init(GICC_BASE, GICD_BASE); 46 } 47 48 void boot_secondary_init_intc(void) 49 { 50 gic_cpu_init(); 51 } 52 53 static TEE_Result rzn1_tz_init(void) 54 { 55 vaddr_t tza_init_reg = 0; 56 vaddr_t tza_targ_reg = 0; 57 58 tza_init_reg = core_mmu_get_va(FW_STATIC_TZA_INIT, MEM_AREA_IO_SEC, 59 sizeof(uint32_t)); 60 tza_targ_reg = core_mmu_get_va(FW_STATIC_TZA_TARG, MEM_AREA_IO_SEC, 61 sizeof(uint32_t)); 62 63 /* TZ initiator ports */ 64 io_write32(tza_init_reg, TZ_INIT_CSA_SEC | TZ_INIT_YS_SEC | 65 TZ_INIT_YC_SEC | TZ_INIT_YD_SEC); 66 67 /* TZ target ports */ 68 io_write32(tza_targ_reg, TZ_TARG_PC_SEC | TZ_TARG_QB_SEC | 69 TZ_TARG_QA_SEC | TZ_TARG_UB_SEC | 70 TZ_TARG_UA_SEC); 71 72 return TEE_SUCCESS; 73 } 74 75 service_init(rzn1_tz_init); 76 77 #ifdef CFG_BOOT_CM3 78 static TEE_Result rzn1_cm3_start(void) 79 { 80 vaddr_t cm3_pwrctrl_reg = 0; 81 vaddr_t cm3_pwrstat_reg = 0; 82 uint64_t timeout_ack = timeout_init_us(IDLE_ACK_TIMEOUT_US); 83 84 cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC, 85 sizeof(uint32_t)); 86 cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC, 87 sizeof(uint32_t)); 88 89 /* Master Idle Request to the interconnect for CM3 */ 90 io_clrbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_MIREQ_A); 91 92 /* Wait for Master Idle Request Acknowledge for CM3 */ 93 while (!timeout_elapsed(timeout_ack)) 94 if (!(io_read32(cm3_pwrstat_reg) & 95 SYSCTRL_PWRSTAT_CM3_MIRACK_A)) 96 break; 97 98 if (io_read32(cm3_pwrstat_reg) & SYSCTRL_PWRSTAT_CM3_MIRACK_A) 99 panic(); 100 101 /* Clock Enable for CM3_HCLK & Active low Reset to CM3 */ 102 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_CLKEN_A); 103 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_RSTN_A); 104 105 return TEE_SUCCESS; 106 } 107 108 service_init(rzn1_cm3_start); 109 #endif 110