1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017, Schneider Electric 4 * Copyright (c) 2020, Linaro Limited 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/ns16550.h> 11 #include <kernel/boot.h> 12 #include <kernel/interrupt.h> 13 #include <kernel/panic.h> 14 #include <mm/core_memprot.h> 15 #include <mm/core_mmu.h> 16 #include <platform_config.h> 17 #include <rzn1_tz.h> 18 19 static struct gic_data gic_data; 20 static struct ns16550_data console_data; 21 22 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 23 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE); 24 register_ddr(DRAM_BASE, DRAM_SIZE); 25 26 void console_init(void) 27 { 28 ns16550_init(&console_data, CONSOLE_UART_BASE, IO_WIDTH_U32, 2); 29 register_serial_console(&console_data.chip); 30 } 31 32 void main_init_gic(void) 33 { 34 vaddr_t gicc_base = 0; 35 vaddr_t gicd_base = 0; 36 37 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, 1); 38 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, 1); 39 if (!gicc_base || !gicd_base) 40 panic(); 41 42 gic_init(&gic_data, gicc_base, gicd_base); 43 44 itr_init(&gic_data.chip); 45 } 46 47 void main_secondary_init_gic(void) 48 { 49 gic_cpu_init(&gic_data); 50 } 51 52 static TEE_Result rzn1_tz_init(void) 53 { 54 vaddr_t tza_init_reg = 0; 55 vaddr_t tza_targ_reg = 0; 56 57 tza_init_reg = core_mmu_get_va(FW_STATIC_TZA_INIT, MEM_AREA_IO_SEC, 58 sizeof(uint32_t)); 59 tza_targ_reg = core_mmu_get_va(FW_STATIC_TZA_TARG, MEM_AREA_IO_SEC, 60 sizeof(uint32_t)); 61 62 /* TZ initiator ports */ 63 io_write32(tza_init_reg, TZ_INIT_CSA_SEC | TZ_INIT_YS_SEC | 64 TZ_INIT_YC_SEC | TZ_INIT_YD_SEC); 65 66 /* TZ target ports */ 67 io_write32(tza_targ_reg, TZ_TARG_PC_SEC | TZ_TARG_QB_SEC | 68 TZ_TARG_QA_SEC | TZ_TARG_UB_SEC | 69 TZ_TARG_UA_SEC); 70 71 return TEE_SUCCESS; 72 } 73 74 service_init(rzn1_tz_init); 75