1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017, Schneider Electric 4 * Copyright (c) 2020, Linaro Limited 5 */ 6 7 #include <arm.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/ns16550.h> 11 #include <kernel/boot.h> 12 #include <kernel/delay.h> 13 #include <kernel/interrupt.h> 14 #include <kernel/panic.h> 15 #include <mm/core_memprot.h> 16 #include <mm/core_mmu.h> 17 #include <platform_config.h> 18 #include <rzn1_tz.h> 19 20 #define SYSCTRL_PWRCTRL_CM3 (SYSCTRL_BASE + 0x174) 21 #define SYSCTRL_PWRSTAT_CM3 (SYSCTRL_BASE + 0x178) 22 23 #define SYSCTRL_PWRCTRL_CM3_CLKEN_A BIT(0) 24 #define SYSCTRL_PWRCTRL_CM3_RSTN_A BIT(1) 25 #define SYSCTRL_PWRCTRL_CM3_MIREQ_A BIT(2) 26 27 #define SYSCTRL_PWRSTAT_CM3_MIRACK_A BIT(0) 28 29 /* Timeout waiting for Master Idle Request Acknowledge */ 30 #define IDLE_ACK_TIMEOUT_US 1000 31 32 static struct gic_data gic_data; 33 static struct ns16550_data console_data; 34 35 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 36 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE); 37 register_ddr(DRAM_BASE, DRAM_SIZE); 38 39 void console_init(void) 40 { 41 ns16550_init(&console_data, CONSOLE_UART_BASE, IO_WIDTH_U32, 2); 42 register_serial_console(&console_data.chip); 43 } 44 45 void main_init_gic(void) 46 { 47 vaddr_t gicc_base = 0; 48 vaddr_t gicd_base = 0; 49 50 gicc_base = (vaddr_t)phys_to_virt(GICC_BASE, MEM_AREA_IO_SEC, 1); 51 gicd_base = (vaddr_t)phys_to_virt(GICD_BASE, MEM_AREA_IO_SEC, 1); 52 if (!gicc_base || !gicd_base) 53 panic(); 54 55 gic_init(&gic_data, gicc_base, gicd_base); 56 57 itr_init(&gic_data.chip); 58 } 59 60 void main_secondary_init_gic(void) 61 { 62 gic_cpu_init(&gic_data); 63 } 64 65 static TEE_Result rzn1_tz_init(void) 66 { 67 vaddr_t tza_init_reg = 0; 68 vaddr_t tza_targ_reg = 0; 69 70 tza_init_reg = core_mmu_get_va(FW_STATIC_TZA_INIT, MEM_AREA_IO_SEC, 71 sizeof(uint32_t)); 72 tza_targ_reg = core_mmu_get_va(FW_STATIC_TZA_TARG, MEM_AREA_IO_SEC, 73 sizeof(uint32_t)); 74 75 /* TZ initiator ports */ 76 io_write32(tza_init_reg, TZ_INIT_CSA_SEC | TZ_INIT_YS_SEC | 77 TZ_INIT_YC_SEC | TZ_INIT_YD_SEC); 78 79 /* TZ target ports */ 80 io_write32(tza_targ_reg, TZ_TARG_PC_SEC | TZ_TARG_QB_SEC | 81 TZ_TARG_QA_SEC | TZ_TARG_UB_SEC | 82 TZ_TARG_UA_SEC); 83 84 return TEE_SUCCESS; 85 } 86 87 service_init(rzn1_tz_init); 88 89 #ifdef CFG_BOOT_CM3 90 static TEE_Result rzn1_cm3_start(void) 91 { 92 vaddr_t cm3_pwrctrl_reg = 0; 93 vaddr_t cm3_pwrstat_reg = 0; 94 uint64_t timeout_ack = timeout_init_us(IDLE_ACK_TIMEOUT_US); 95 96 cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC, 97 sizeof(uint32_t)); 98 cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC, 99 sizeof(uint32_t)); 100 101 /* Master Idle Request to the interconnect for CM3 */ 102 io_clrbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_MIREQ_A); 103 104 /* Wait for Master Idle Request Acknowledge for CM3 */ 105 while (!timeout_elapsed(timeout_ack)) 106 if (!(io_read32(cm3_pwrstat_reg) & 107 SYSCTRL_PWRSTAT_CM3_MIRACK_A)) 108 break; 109 110 if (io_read32(cm3_pwrstat_reg) & SYSCTRL_PWRSTAT_CM3_MIRACK_A) 111 panic(); 112 113 /* Clock Enable for CM3_HCLK & Active low Reset to CM3 */ 114 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_CLKEN_A); 115 io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_RSTN_A); 116 117 return TEE_SUCCESS; 118 } 119 120 service_init(rzn1_cm3_start); 121 #endif 122