1 /* 2 * Copyright (C) 2017, Fuzhou Rockchip Electronics Co., Ltd. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <common.h> 29 #include <console.h> 30 #include <cru.h> 31 #include <grf.h> 32 #include <initcall.h> 33 #include <io.h> 34 #include <kernel/delay.h> 35 #include <kernel/generic_boot.h> 36 #include <kernel/misc.h> 37 #include <kernel/panic.h> 38 #include <mm/core_mmu.h> 39 #include <mm/core_memprot.h> 40 #include <platform_config.h> 41 #include <sm/optee_smc.h> 42 #include <sm/psci.h> 43 #include <stdint.h> 44 #include <tee/entry_std.h> 45 #include <tee/entry_fast.h> 46 47 struct dram_data { 48 uint32_t cru_mode_con; 49 uint32_t cru_clksel0; 50 uint32_t cru_clksel1; 51 uint32_t cru_clksel10; 52 uint32_t cru_clksel21; 53 uint32_t cru_clkgate[CRU_CLKGATE_CON_CNT]; 54 }; 55 56 static struct dram_data dram_d; 57 58 static const uint32_t clks_gating_table[CRU_CLKGATE_CON_CNT] = { 59 /* gate: 0-3 */ 60 0xefb8, 61 0x0ff7, 62 0xfff4, 63 0x887f, 64 /* gate: 4-7 */ 65 0x0030, 66 0x00f8, 67 0x07e0, 68 0xc000, 69 /* gate: 8-11 */ 70 0xff84, 71 0xb047, 72 0x1ca0, 73 0x57ff, 74 /* gate: 12-15 */ 75 0x0000, 76 0x00ff, 77 0x1cc0, 78 0x000f, 79 }; 80 81 static void clks_disable(void) 82 { 83 uint32_t i; 84 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 85 86 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++) { 87 dram_d.cru_clkgate[i] = read32(va_base + CRU_CLKGATE_CON(i)); 88 write32(BITS_WITH_WMASK(clks_gating_table[i], 0xffff, 0), 89 va_base + CRU_CLKGATE_CON(i)); 90 } 91 } 92 93 static void clks_restore(void) 94 { 95 uint32_t i; 96 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 97 98 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++) 99 write32(BITS_WITH_WMASK(dram_d.cru_clkgate[i], 0xffff, 0), 100 va_base + CRU_CLKGATE_CON(i)); 101 } 102 103 static void pll_power_down(uint32_t pll) 104 { 105 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 106 107 write32(PLL_SLOW_MODE(pll), va_base + CRU_MODE_CON); 108 write32(PLL_POWER_DOWN, va_base + CRU_PLL_CON1(pll)); 109 } 110 111 static void pll_power_up(uint32_t pll) 112 { 113 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 114 115 write32(PLL_POWER_UP, va_base + CRU_PLL_CON1(pll)); 116 } 117 118 static void pll_wait_lock(uint32_t pll) 119 { 120 uint32_t loop = 0; 121 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 122 123 while (!(read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK) && 124 (loop < 500)) { 125 udelay(2); 126 loop++; 127 } 128 129 if (!(read32(va_base + CRU_PLL_CON1(pll)) & PLL_LOCK)) { 130 EMSG("PLL can't lock, index = %" PRIu32, pll); 131 panic(); 132 } 133 } 134 135 /* 136 * Select clock from external 24MHz OSC(slow mode) and power down plls, 137 * then set frequency division of relevant bus to 24MHz. 138 */ 139 static void plls_power_down(void) 140 { 141 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 142 143 dram_d.cru_clksel0 = read32(va_base + CRU_CLKSEL_CON(0)); 144 dram_d.cru_clksel1 = read32(va_base + CRU_CLKSEL_CON(1)); 145 dram_d.cru_clksel10 = read32(va_base + CRU_CLKSEL_CON(10)); 146 dram_d.cru_clksel21 = read32(va_base + CRU_CLKSEL_CON(21)); 147 dram_d.cru_mode_con = read32(va_base + CRU_MODE_CON); 148 149 pll_power_down(GPLL_ID); 150 pll_power_down(CPLL_ID); 151 pll_power_down(APLL_ID); 152 153 /* core */ 154 write32(BITS_WITH_WMASK(0, 0x1f, 0), va_base + CRU_CLKSEL_CON(0)); 155 write32(BITS_WITH_WMASK(0, 0xf, 0) | BITS_WITH_WMASK(0, 0x7, 4), 156 va_base + CRU_CLKSEL_CON(1)); 157 158 /* peri aclk, hclk, pclk */ 159 write32(BITS_WITH_WMASK(0, 0x1f, 0) | BITS_WITH_WMASK(0, 0x3, 8) | 160 BITS_WITH_WMASK(0, 0x7, 12), 161 va_base + CRU_CLKSEL_CON(10)); 162 163 /* pdbus */ 164 write32(BITS_WITH_WMASK(0, 0x1f, 8), va_base + CRU_CLKSEL_CON(0)); 165 write32(BITS_WITH_WMASK(0, 0x3, 8) | BITS_WITH_WMASK(0, 0x7, 12), 166 va_base + CRU_CLKSEL_CON(1)); 167 168 /* hdmi cec 32k */ 169 write32(BITS_WITH_WMASK(732, 0x3fff, 0) | BITS_WITH_WMASK(2, 0x3, 14), 170 va_base + CRU_CLKSEL_CON(21)); 171 } 172 173 static void plls_restore(void) 174 { 175 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 176 177 /* power up plls */ 178 pll_power_up(APLL_ID); 179 pll_power_up(GPLL_ID); 180 pll_power_up(CPLL_ID); 181 182 udelay(200); 183 184 /* wait lock*/ 185 pll_wait_lock(APLL_ID); 186 pll_wait_lock(GPLL_ID); 187 pll_wait_lock(CPLL_ID); 188 189 /* hdmi cec 32k */ 190 write32(dram_d.cru_clksel21 | BITS_WMSK(0x3fff, 0) | BITS_WMSK(0x3, 14), 191 va_base + CRU_CLKSEL_CON(21)); 192 193 /* pdbus */ 194 write32(dram_d.cru_clksel0 | BITS_WMSK(0x1f, 8), 195 va_base + CRU_CLKSEL_CON(0)); 196 write32(dram_d.cru_clksel1 | BITS_WMSK(0x3, 8) | BITS_WMSK(0x7, 12), 197 va_base + CRU_CLKSEL_CON(1)); 198 199 /* peri aclk, hclk, pclk */ 200 write32(dram_d.cru_clksel10 | BITS_WMSK(0x1f, 0) | BITS_WMSK(0x3, 8) | 201 BITS_WMSK(0x7, 12), 202 va_base + CRU_CLKSEL_CON(10)); 203 204 /* core */ 205 write32(dram_d.cru_clksel0 | BITS_WMSK(0x1f, 0), 206 va_base + CRU_CLKSEL_CON(0)); 207 write32(dram_d.cru_clksel1 | BITS_WMSK(0xf, 0) | BITS_WMSK(0x7, 4), 208 va_base + CRU_CLKSEL_CON(1)); 209 210 /* resume plls mode */ 211 write32(dram_d.cru_mode_con | BITS_WMSK(0x1, PLL_MODE_BIT(APLL_ID)), 212 va_base + CRU_MODE_CON); 213 write32(dram_d.cru_mode_con | BITS_WMSK(0x1, PLL_MODE_BIT(CPLL_ID)), 214 va_base + CRU_MODE_CON); 215 write32(dram_d.cru_mode_con | BITS_WMSK(0x1, PLL_MODE_BIT(GPLL_ID)), 216 va_base + CRU_MODE_CON); 217 } 218 219 static bool wait_core_wfe_i(uint32_t core) 220 { 221 uint32_t wfei_mask, loop = 0; 222 vaddr_t va_base = (vaddr_t)phys_to_virt_io(GRF_BASE); 223 224 wfei_mask = CORE_WFE_I_MASK(core); 225 while (!(read32(va_base + GRF_CPU_STATUS1) & wfei_mask) && loop < 500) { 226 udelay(2); 227 loop++; 228 } 229 230 return read32(va_base + GRF_CPU_STATUS1) & wfei_mask; 231 } 232 233 static bool core_held_in_reset(uint32_t core) 234 { 235 uint32_t val; 236 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 237 238 val = read32(va_base + CRU_SOFTRST_CON(0)); 239 240 return val & CORE_HELD_IN_RESET(core); 241 } 242 243 uint32_t psci_version(void) 244 { 245 return PSCI_VERSION_1_0; 246 } 247 248 int psci_features(uint32_t psci_fid) 249 { 250 switch (psci_fid) { 251 case PSCI_PSCI_FEATURES: 252 case PSCI_VERSION: 253 case PSCI_CPU_ON: 254 case PSCI_CPU_OFF: 255 case PSCI_SYSTEM_SUSPEND: 256 case PSCI_SYSTEM_RESET: 257 return PSCI_RET_SUCCESS; 258 default: 259 return PSCI_RET_NOT_SUPPORTED; 260 } 261 } 262 263 int psci_cpu_on(uint32_t core_idx, uint32_t entry, 264 uint32_t context_id __unused) 265 { 266 bool wfei; 267 vaddr_t cru_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 268 vaddr_t isram_base = (vaddr_t)phys_to_virt_io(ISRAM_BASE); 269 270 core_idx &= MPIDR_CPU_MASK; 271 if ((core_idx == 0) || (core_idx >= CFG_TEE_CORE_NB_CORE)) 272 return PSCI_RET_INVALID_PARAMETERS; 273 274 DMSG("core_id: %" PRIu32, core_idx); 275 276 /* set secondary cores' NS entry addresses */ 277 ns_entry_addrs[core_idx] = entry; 278 279 /* wait */ 280 if (!core_held_in_reset(core_idx)) { 281 wfei = wait_core_wfe_i(core_idx); 282 if (!wfei) { 283 EMSG("Can't wait cpu%" PRIu32 " wfei before softrst", 284 core_idx); 285 return PSCI_RET_DENIED; 286 } 287 } 288 289 /* soft reset core */ 290 write32(CORE_SOFT_RESET(core_idx), cru_base + CRU_SOFTRST_CON(0)); 291 dsb(); 292 293 udelay(2); 294 295 /* soft release core */ 296 write32(CORE_SOFT_RELEASE(core_idx), cru_base + CRU_SOFTRST_CON(0)); 297 dsb(); 298 299 /* wait */ 300 wfei = wait_core_wfe_i(core_idx); 301 if (!wfei) { 302 EMSG("Can't wait cpu%" PRIu32 " wfei after softrst", core_idx); 303 return PSCI_RET_DENIED; 304 } 305 306 /* set secondary secure entry address and lock tag */ 307 write32(CFG_TEE_LOAD_ADDR, isram_base + BOOT_ADDR_OFFSET); 308 write32(LOCK_TAG, isram_base + LOCK_ADDR_OFFSET); 309 dsb(); 310 311 sev(); 312 dsb(); 313 314 return PSCI_RET_SUCCESS; 315 } 316 317 int psci_cpu_off(void) 318 { 319 uint32_t core = get_core_pos(); 320 321 if ((core == 0) || (core >= CFG_TEE_CORE_NB_CORE)) 322 return PSCI_RET_INVALID_PARAMETERS; 323 324 DMSG("core_id: %" PRIu32, core); 325 326 psci_armv7_cpu_off(); 327 thread_mask_exceptions(THREAD_EXCP_ALL); 328 329 while (1) 330 wfi(); 331 332 return PSCI_RET_INTERNAL_FAILURE; 333 } 334 335 int psci_affinity_info(uint32_t affinity, 336 uint32_t lowest_affnity_level __unused) 337 { 338 uint32_t core_idx = affinity & MPIDR_CPU_MASK; 339 uint32_t wfi_mask = CORE_WFI_MASK(core_idx); 340 vaddr_t va_base = (vaddr_t)phys_to_virt_io(GRF_BASE); 341 342 DMSG("core_id: %" PRIu32 " STATUS: %" PRIx32 " MASK: %" PRIx32, 343 core_idx, read32(va_base + GRF_CPU_STATUS1), wfi_mask); 344 345 return (read32(va_base + GRF_CPU_STATUS1) & wfi_mask) ? 346 PSCI_AFFINITY_LEVEL_OFF : PSCI_AFFINITY_LEVEL_ON; 347 } 348 349 void psci_system_reset(void) 350 { 351 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 352 353 /* PLLs enter slow mode */ 354 write32(PLLS_SLOW_MODE, va_base + CRU_MODE_CON); 355 dsb(); 356 357 /* Global second reset */ 358 write32(CRU_SNDRST_VAL, va_base + CRU_SNDRST_VAL_BASE); 359 dsb(); 360 } 361 362 int psci_system_suspend(uintptr_t entry __unused, 363 uint32_t context_id __unused, 364 struct sm_nsec_ctx *nsec __unused) 365 { 366 DMSG("system suspend"); 367 368 clks_disable(); 369 plls_power_down(); 370 371 cache_op_inner(DCACHE_CLEAN_INV, NULL, 0); 372 373 wfi(); 374 375 plls_restore(); 376 clks_restore(); 377 378 return PSCI_RET_SUCCESS; 379 } 380 381 /* When SMP bootup, we release cores one by one */ 382 static TEE_Result reset_nonboot_cores(void) 383 { 384 vaddr_t va_base = (vaddr_t)phys_to_virt_io(CRU_BASE); 385 386 write32(NONBOOT_CORES_SOFT_RESET, va_base + CRU_SOFTRST_CON(0)); 387 388 return TEE_SUCCESS; 389 } 390 391 service_init_late(reset_nonboot_cores); 392