1 /* 2 * Copyright (c) 2016, GlobalLogic 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <console.h> 29 #include <kernel/generic_boot.h> 30 #include <kernel/panic.h> 31 #include <kernel/pm_stubs.h> 32 #include <mm/core_memprot.h> 33 #include <platform_config.h> 34 #include <stdint.h> 35 #include <tee/entry_std.h> 36 #include <tee/entry_fast.h> 37 #include <drivers/scif.h> 38 #include <drivers/gic.h> 39 40 register_phys_mem(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE); 41 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 42 register_phys_mem(MEM_AREA_IO_SEC, GICC_BASE, GIC_DIST_REG_SIZE); 43 44 register_nsec_ddr(NSEC_DDR_0_BASE, NSEC_DDR_0_SIZE); 45 register_nsec_ddr(NSEC_DDR_1_BASE, NSEC_DDR_1_SIZE); 46 #ifdef NSEC_DDR_2_BASE 47 register_nsec_ddr(NSEC_DDR_2_BASE, NSEC_DDR_2_SIZE); 48 #endif 49 #ifdef NSEC_DDR_3_BASE 50 register_nsec_ddr(NSEC_DDR_3_BASE, NSEC_DDR_3_SIZE); 51 #endif 52 53 static void main_fiq(void); 54 55 static const struct thread_handlers handlers = { 56 .std_smc = tee_entry_std, 57 .fast_smc = tee_entry_fast, 58 .nintr = main_fiq, 59 .cpu_on = cpu_on_handler, 60 .cpu_off = pm_do_nothing, 61 .cpu_suspend = pm_do_nothing, 62 .cpu_resume = pm_do_nothing, 63 .system_off = pm_do_nothing, 64 .system_reset = pm_do_nothing, 65 }; 66 67 static struct scif_uart_data console_data; 68 69 const struct thread_handlers *generic_boot_get_handlers(void) 70 { 71 return &handlers; 72 } 73 74 static void main_fiq(void) 75 { 76 panic(); 77 } 78 79 void console_init(void) 80 { 81 scif_uart_init(&console_data, CONSOLE_UART_BASE); 82 register_serial_console(&console_data.chip); 83 } 84