xref: /optee_os/core/arch/arm/plat-rcar/main.c (revision 4edd96e6d7a7228e907cf498b23e5b5fbdaf39a0)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2016, GlobalLogic
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright notice,
10  * this list of conditions and the following disclaimer.
11  *
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  * this list of conditions and the following disclaimer in the documentation
14  * and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
20  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26  * POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <console.h>
30 #include <crypto/crypto.h>
31 #include <kernel/boot.h>
32 #include <kernel/panic.h>
33 #include <mm/core_memprot.h>
34 #include <platform_config.h>
35 #include <stdint.h>
36 #include <drivers/scif.h>
37 #include <drivers/gic.h>
38 
39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE);
40 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
41 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICC_BASE, GIC_CPU_REG_SIZE);
42 #ifdef PRR_BASE
43 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PRR_BASE, SMALL_PAGE_SIZE);
44 #endif
45 
46 /* Legacy platforms */
47 #if defined(PLATFORM_FLAVOR_salvator_h3) || \
48 	defined(PLATFORM_FLAVOR_salvator_h3_4x2g) || \
49 	defined(PLATFORM_FLAVOR_salvator_m3) || \
50 	defined(PLATFORM_FLAVOR_salvator_m3_2x4g) || \
51 	defined(PLATFORM_FLAVOR_spider_s4)
52 register_ddr(NSEC_DDR_0_BASE, NSEC_DDR_0_SIZE);
53 register_ddr(NSEC_DDR_1_BASE, NSEC_DDR_1_SIZE);
54 #ifdef NSEC_DDR_2_BASE
55 register_ddr(NSEC_DDR_2_BASE, NSEC_DDR_2_SIZE);
56 #endif
57 #ifdef NSEC_DDR_3_BASE
58 register_ddr(NSEC_DDR_3_BASE, NSEC_DDR_3_SIZE);
59 #endif
60 #endif
61 
62 static struct scif_uart_data console_data __nex_bss;
63 
64 #ifdef PRR_BASE
65 uint32_t rcar_prr_value __nex_bss;
66 #endif
67 
68 void console_init(void)
69 {
70 	scif_uart_init(&console_data, CONSOLE_UART_BASE);
71 	register_serial_console(&console_data.chip);
72 }
73 
74 #ifdef CFG_RCAR_ROMAPI
75 /* Should only seed from a hardware random number generator */
76 static_assert(!IS_ENABLED(CFG_WITH_SOFTWARE_PRNG));
77 
78 unsigned long plat_get_aslr_seed(void)
79 {
80 	unsigned long seed = 0;
81 
82 	/* On RCAR we can get hw random bytes on early boot stages */
83 	if (crypto_rng_read(&seed, sizeof(seed)))
84 		panic();
85 
86 	return seed;
87 }
88 #endif
89 
90 void boot_primary_init_intc(void)
91 {
92 	gic_init(GICC_BASE, GICD_BASE);
93 }
94 
95 void boot_secondary_init_intc(void)
96 {
97 	gic_cpu_init();
98 }
99