xref: /optee_os/core/arch/arm/plat-qcom/main.c (revision fedadb6460b1ea7db709c6f5a0572f5a8cb8e5c9)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (c) 2025, Linaro Limited
4  * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5  */
6 
7 #include <console.h>
8 #include <drivers/gic.h>
9 #include <drivers/qcom_geni_uart.h>
10 #include <kernel/boot.h>
11 #include <mm/core_mmu.h>
12 #include <platform_config.h>
13 
14 /*
15  * Register the physical memory area for peripherals etc. Here we are
16  * registering the UART console.
17  */
18 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GENI_UART_REG_BASE,
19 			GENI_UART_REG_SIZE);
20 
21 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
22 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICR_BASE, GIC_DIST_REG_SIZE);
23 
24 #if defined(PLATFORM_FLAVOR_kodiak)
25 register_phys_mem(MEM_AREA_IO_NSEC, WPSS_BASE, CORE_MMU_PGDIR_SIZE);
26 register_phys_mem(MEM_AREA_IO_NSEC, TURING_BASE, TURING_SIZE);
27 register_phys_mem(MEM_AREA_IO_NSEC, LPASS_BASE, LPASS_SIZE);
28 register_phys_mem(MEM_AREA_IO_NSEC, IRIS_BASE, IRIS_SIZE);
29 #endif
30 
31 register_ddr(DRAM0_BASE, DRAM0_SIZE);
32 #ifdef DRAM1_BASE
33 register_ddr(DRAM1_BASE, DRAM1_SIZE);
34 #endif
35 
36 static struct qcom_geni_uart_data console_data;
37 
38 void plat_console_init(void)
39 {
40 	qcom_geni_uart_init(&console_data, GENI_UART_REG_BASE);
41 	register_serial_console(&console_data.chip);
42 }
43 
44 static TEE_Result platform_banner(void)
45 {
46 	IMSG("Platform Qualcomm: Flavor %s", TO_STR(PLATFORM_FLAVOR));
47 
48 	return TEE_SUCCESS;
49 }
50 
51 boot_final(platform_banner);
52 
53 void boot_primary_init_intc(void)
54 {
55 	gic_init_v3(0, GICD_BASE, GICR_BASE);
56 }
57 
58 void boot_secondary_init_intc(void)
59 {
60 	gic_init_per_cpu();
61 }
62