xref: /optee_os/core/arch/arm/plat-k3/drivers/ti_sci_protocol.h (revision 6b817698e4456fafb89fdebe5c47b3d64d993385)
1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (C) 2016-2022 Texas Instruments Incorporated - https://www.ti.com/
4  *	Lokesh Vutla <lokeshvutla@ti.com>
5  *	Manorit Chawdhry <m-chawdhry@ti.com>
6  */
7 
8 #ifndef TI_SCI_PROTOCOL_H
9 #define TI_SCI_PROTOCOL_H
10 
11 #include <compiler.h>
12 #include <stdint.h>
13 #include <util.h>
14 
15 /* Generic Messages */
16 #define TI_SCI_MSG_VERSION               0x0002
17 
18 /* Device requests */
19 #define TI_SCI_MSG_SET_DEVICE_STATE      0x0200
20 
21 /* Security Management Messages */
22 #define TI_SCI_MSG_FWL_SET               0x9000
23 #define TI_SCI_MSG_FWL_GET               0x9001
24 #define TI_SCI_MSG_FWL_CHANGE_OWNER      0x9002
25 #define TI_SCI_MSG_SA2UL_GET_DKEK        0x9029
26 #define TI_SCI_MSG_READ_OTP_MMR          0x9022
27 #define TI_SCI_MSG_WRITE_OTP_ROW         0x9023
28 #define TI_SCI_MSG_LOCK_OTP_ROW          0x9024
29 
30 /* OTP Revision Read/Write Message Description */
31 #define TI_SCI_MSG_WRITE_SWREV           0x9032
32 #define TI_SCI_MSG_READ_SWREV            0x9033
33 #define TI_SCI_MSG_READ_KEYCNT_KEYREV    0x9034
34 #define TI_SCI_MSG_WRITE_KEYREV          0x9035
35 
36 /**
37  * struct ti_sci_secure_msg_hdr - Secure Message Header for All messages
38  *				 and responses
39  *
40  * @checksum:	Integrity check for HS devices
41  * @reserved:	Reserved for future uses
42  */
43 struct ti_sci_secure_msg_hdr {
44 	uint16_t checksum;
45 	uint16_t reserved;
46 } __packed;
47 
48 /**
49  * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
50  * @type:	Type of messages: One of TI_SCI_MSG* values
51  * @host:	Host of the message
52  * @seq:	Message identifier indicating a transfer sequence
53  * @flags:	Flag for the message
54  */
55 struct ti_sci_msg_hdr {
56 	struct ti_sci_secure_msg_hdr sec_hdr;
57 	uint16_t type;
58 	uint8_t host;
59 	uint8_t seq;
60 #define TI_SCI_MSG_FLAG(val)			BIT(val)
61 #define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE	0x0
62 #define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED		TI_SCI_MSG_FLAG(0)
63 #define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED	TI_SCI_MSG_FLAG(1)
64 #define TI_SCI_FLAG_RESP_GENERIC_NACK		0x0
65 #define TI_SCI_FLAG_RESP_GENERIC_ACK		TI_SCI_MSG_FLAG(1)
66 	/* Additional Flags */
67 	uint32_t flags;
68 } __packed;
69 
70 /**
71  * struct ti_sci_msg_version_req - Request for firmware version information
72  * @hdr:	Generic header
73  *
74  * Request for TI_SCI_MSG_VERSION
75  */
76 struct ti_sci_msg_req_version {
77 	struct ti_sci_msg_hdr hdr;
78 } __packed;
79 
80 /**
81  * struct ti_sci_msg_resp_version - Response for firmware version information
82  * @hdr:		Generic header
83  * @firmware_description: String describing the firmware
84  * @firmware_revision:	Firmware revision
85  * @abi_major:		Major version of the ABI that firmware supports
86  * @abi_minor:		Minor version of the ABI that firmware supports
87  * @sub_version:	Sub-version number of the firmware
88  * @patch_version:	Patch-version number of the firmware.
89  *
90  * In general, ABI version changes follow the rule that minor version increments
91  * are backward compatible. Major revision changes in ABI may not be
92  * backward compatible.
93  *
94  * Response to request TI_SCI_MSG_VERSION
95  */
96 struct ti_sci_msg_resp_version {
97 	struct ti_sci_msg_hdr hdr;
98 #define FIRMWARE_DESCRIPTION_LENGTH 32
99 	char firmware_description[FIRMWARE_DESCRIPTION_LENGTH];
100 	uint16_t firmware_revision;
101 	uint8_t abi_major;
102 	uint8_t abi_minor;
103 	uint8_t sub_version;
104 	uint8_t patch_version;
105 } __packed;
106 
107 /**
108  * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
109  * @hdr:	Generic header
110  * @id:		Indicates which device to modify
111  * @reserved:	Reserved space in message, must be 0 for backward compatibility
112  * @state:	The desired state of the device.
113  *
114  * Certain flags can also be set to alter the device state:
115  * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
116  * The meaning of this flag will vary slightly from device to device and from
117  * SoC to SoC but it generally allows the device to wake the SoC out of deep
118  * suspend states.
119  * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
120  * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
121  * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
122  * If another host already has this device set to STATE_RETENTION or STATE_ON,
123  * the message will fail. Once successful, other hosts attempting to set
124  * STATE_RETENTION or STATE_ON will fail.
125  *
126  * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
127  * ACK/NACK message.
128  */
129 struct ti_sci_msg_req_set_device_state {
130 	/* Additional hdr->flags options */
131 #define MSG_FLAG_DEVICE_WAKE_ENABLED	TI_SCI_MSG_FLAG(8)
132 #define MSG_FLAG_DEVICE_RESET_ISO	TI_SCI_MSG_FLAG(9)
133 #define MSG_FLAG_DEVICE_EXCLUSIVE	TI_SCI_MSG_FLAG(10)
134 	struct ti_sci_msg_hdr hdr;
135 	uint32_t id;
136 	uint32_t reserved;
137 
138 #define MSG_DEVICE_SW_STATE_AUTO_OFF	0
139 #define MSG_DEVICE_SW_STATE_RETENTION	1
140 #define MSG_DEVICE_SW_STATE_ON		2
141 	uint8_t state;
142 } __packed;
143 
144 /**
145  * struct ti_sci_msg_resp_set_device_state - Response for set device state
146  * @hdr:	Generic header
147  *
148  * Response to request TI_SCI_MSG_SET_DEVICE_STATE
149  */
150 struct ti_sci_msg_resp_set_device_state {
151 	struct ti_sci_msg_hdr hdr;
152 } __packed;
153 
154 #define FWL_MAX_PRIVID_SLOTS 3U
155 
156 /**
157  * struct ti_sci_msg_req_fwl_set_firewall_region - Set firewall permissions
158  * @hdr:		Generic Header
159  * @fwl_id:		Firewall ID
160  * @region:		Region or channel number to set config info.
161  *			This field is unused in case of a simple firewall and
162  *			must be initialized to zero.  In case of a region based
163  *			firewall, this field indicates the region (index
164  *			starting from 0). In case of a channel based firewall,
165  *			this field indicates the channel (index starting
166  *			from 0).
167  * @n_permission_regs:	Number of permission registers to set
168  * @control:		Contents of the firewall CONTROL register to set
169  * @permissions:	Contents of the firewall PERMISSION register to set
170  * @start_address:	Contents of the firewall START_ADDRESS register to set
171  * @end_address:	Contents of the firewall END_ADDRESS register to set
172  */
173 struct ti_sci_msg_req_fwl_set_firewall_region {
174 	struct ti_sci_msg_hdr hdr;
175 	uint16_t fwl_id;
176 	uint16_t region;
177 	uint32_t n_permission_regs;
178 	uint32_t control;
179 	uint32_t permissions[FWL_MAX_PRIVID_SLOTS];
180 	uint64_t start_address;
181 	uint64_t end_address;
182 } __packed;
183 
184 struct ti_sci_msg_resp_fwl_set_firewall_region {
185 	struct ti_sci_msg_hdr hdr;
186 } __packed;
187 
188 /**
189  * struct ti_sci_msg_req_fwl_get_firewall_region - Retrieve firewall permissions
190  * @hdr:		Generic Header
191  * @fwl_id:		Firewall ID in question
192  * @region:		Region or channel number to set config info.
193  *			This field is unused in case of a simple firewall and
194  *			must be initialized to zero.  In case of a region based
195  *			firewall, this field indicates the region (index
196  *			starting from 0). In case of a channel based firewall,
197  *			this field indicates the channel (index starting
198  *			from 0).
199  * @n_permission_regs:	Number of permission registers to retrieve
200  */
201 struct ti_sci_msg_req_fwl_get_firewall_region {
202 	struct ti_sci_msg_hdr hdr;
203 	uint16_t fwl_id;
204 	uint16_t region;
205 	uint32_t n_permission_regs;
206 } __packed;
207 
208 /**
209  * struct ti_sci_msg_resp_fwl_get_firewall_region - Response for retrieving the
210  *						    firewall permissions
211  *
212  * @hdr:		Generic Header
213  *
214  * @fwl_id:		Firewall ID in question
215  * @region:		Region or channel number to set config info.
216  *			This field is unused in case of a simple firewall and
217  *			must be initialized to zero.  In case of a region based
218  *			firewall, this field indicates the region (index
219  *			starting from 0). In case of a channel based firewall,
220  *			this field indicates the channel (index starting
221  *			from 0).
222  * @n_permission_regs:	Number of permission registers retrieved
223  * @control:		Contents of the firewall CONTROL register
224  * @permissions:	Contents of the firewall PERMISSION registers
225  * @start_address:	Contents of the firewall START_ADDRESS register
226  * @end_address:	Contents of the firewall END_ADDRESS register
227  */
228 struct ti_sci_msg_resp_fwl_get_firewall_region {
229 	struct ti_sci_msg_hdr hdr;
230 	uint16_t fwl_id;
231 	uint16_t region;
232 	uint32_t n_permission_regs;
233 	uint32_t control;
234 	uint32_t permissions[FWL_MAX_PRIVID_SLOTS];
235 	uint64_t start_address;
236 	uint64_t end_address;
237 } __packed;
238 
239 /**
240  * struct ti_sci_msg_req_fwl_change_owner_info - Request change firewall owner
241  *
242  * @hdr:		Generic Header
243  *
244  * @fwl_id:		Firewall ID in question
245  * @region:		Region or channel number if applicable
246  * @owner_index:	New owner index to transfer ownership to
247  */
248 struct ti_sci_msg_req_fwl_change_owner_info {
249 	struct ti_sci_msg_hdr hdr;
250 	uint16_t fwl_id;
251 	uint16_t region;
252 	uint8_t owner_index;
253 } __packed;
254 
255 /**
256  * struct ti_sci_msg_resp_fwl_change_owner_info - Response for change
257  *						  firewall owner
258  *
259  * @hdr:		Generic Header
260  *
261  * @fwl_id:		Firewall ID specified in request
262  * @region:		Region or channel number specified in request
263  * @owner_index:	Owner index specified in request
264  * @owner_privid:	New owner priv-ID returned by DMSC.
265  * @owner_permission_bits:	New owner permission bits returned by DMSC.
266  */
267 struct ti_sci_msg_resp_fwl_change_owner_info {
268 	struct ti_sci_msg_hdr hdr;
269 	uint16_t fwl_id;
270 	uint16_t region;
271 	uint8_t owner_index;
272 	uint8_t owner_privid;
273 	uint16_t owner_permission_bits;
274 } __packed;
275 
276 /**
277  * struct ti_sci_msg_sa2ul_get_dkek_req - Request for DKEK value
278  * @hdr:			Generic header
279  * @sa2ul_instance:		SA2UL instance number - set to 0
280  * @kdf_label_len:		Length of "Label" input to KDF
281  * @kdf_context_len:		Length of "Context" input to KDF
282  * @kdf_label_and_context:	"Label" and "Context" bytes
283  *
284  * Request for TI_SCI_MSG_SA2UL_GET_DKEK
285  */
286 struct ti_sci_msg_req_sa2ul_get_dkek {
287 	struct ti_sci_msg_hdr hdr;
288 	uint8_t sa2ul_instance;
289 	uint8_t kdf_label_len;
290 	uint8_t kdf_context_len;
291 #define KDF_LABEL_AND_CONTEXT_LEN_MAX 41
292 	uint8_t kdf_label_and_context[KDF_LABEL_AND_CONTEXT_LEN_MAX];
293 } __packed;
294 
295 /**
296  * struct ti_sci_msg_sa2ul_get_dkek_req - Response for DKEK value
297  * @hdr:	Generic header
298  * @dkek:	Array containing Derived KEK
299  *
300  * Response to request TI_SCI_MSG_SA2UL_GET_DKEK
301  */
302 struct ti_sci_msg_resp_sa2ul_get_dkek {
303 	struct ti_sci_msg_hdr hdr;
304 #define SA2UL_DKEK_KEY_LEN 32
305 	uint8_t dkek[SA2UL_DKEK_KEY_LEN];
306 } __packed;
307 
308 /**
309  * struct ti_sci_msg_resp_read_otp_mmr - Request for reading extended OTP
310  * @hdr:	Generic header
311  * @mmr_idx:	Index of 32 bit MMR
312  *
313  * Request for TI_SCI_MSG_READ_OTP_MMR
314  */
315 struct ti_sci_msg_req_read_otp_mmr {
316 	struct ti_sci_msg_hdr hdr;
317 	uint8_t mmr_idx;
318 } __packed;
319 
320 /**
321  * struct ti_sci_msg_resp_read_otp_mmr - Response for reading extended OTP
322  * @hdr:	Generic header
323  * @mmr_val:	Value written in the OTP
324  *
325  * Response to request TI_SCI_MSG_READ_OTP_MMR
326  */
327 struct ti_sci_msg_resp_read_otp_mmr {
328 	struct ti_sci_msg_hdr hdr;
329 	uint32_t mmr_val;
330 } __packed;
331 
332 /**
333  * struct ti_sci_msg_req_write_otp_row - Request for writing Extended OTP
334  * @hdr:	Generic header
335  * @row_idx:		Index of the OTP row. Zero indexing
336  * @row_val:		Value to be written
337  * @row_mask:		Mask bits for row_val to be written
338  *
339  * Request for TI_SCI_MSG_WRITE_OTP_ROW
340  */
341 struct ti_sci_msg_req_write_otp_row {
342 	struct ti_sci_msg_hdr hdr;
343 	uint8_t row_idx;
344 	uint32_t row_val;
345 	uint32_t row_mask;
346 } __packed;
347 
348 /**
349  * struct ti_sci_msg_resp_write_otp_row - Response for writing Extended OTP
350  * @hdr:		Generic header
351  * @row_val:		Value that is written
352  *
353  * Response to request TI_SCI_MSG_WRITE_OTP_ROW
354  */
355 struct ti_sci_msg_resp_write_otp_row {
356 	struct ti_sci_msg_hdr hdr;
357 	uint32_t row_val;
358 } __packed;
359 
360 /**
361  * struct ti_sci_msg_req_lock_otp_row - Request for Lock OTP row
362  * @hdr:		Generic header
363  * @row_idx:		Index of the OTP row. Zero indexing
364  * @hw_write_lock:	0x5A indicates row will be write protected
365  * @hw_read_lock:	0x5A indicates row will be read protected
366  * @row_soft_lock:	Software write lock
367  *
368  * Request for TI_SCI_MSG_LOCK_OTP_ROW
369  */
370 struct ti_sci_msg_req_lock_otp_row {
371 	struct ti_sci_msg_hdr hdr;
372 	uint8_t row_idx;
373 	uint8_t hw_write_lock;
374 	uint8_t hw_read_lock;
375 	uint8_t row_soft_lock;
376 } __packed;
377 
378 /**
379  * struct ti_sci_msg_resp_lock_otp_row - Response for Lock OTP row
380  * @hdr:	Generic header
381  *
382  * Response to request TI_SCI_MSG_LOCK_OTP_ROW
383  */
384 struct ti_sci_msg_resp_lock_otp_row {
385 	struct ti_sci_msg_hdr hdr;
386 } __packed;
387 
388 /**
389  * \brief OTP Revision Identifiers
390  */
391 enum tisci_otp_revision_identifier {
392 	/** Software Revision SBL */
393 	OTP_REV_ID_SBL        = 0,
394 	/** Software Revision SYSFW */
395 	OTP_REV_ID_SYSFW      = 1,
396 	/** Software Revision Secure Board Configuration */
397 	OTP_REV_ID_SEC_BRDCFG = 2,
398 };
399 
400 /**
401  * struct ti_sci_msq_req_set_swrev - Request for writing the Software Revision
402  * in OTP
403  * @hdr:	Generic header
404  * @identifier: One of the entries from enum tisci_otp_revision_identifier
405  * @swrev:	Revision value (integer) to be bit encoded, and programmed
406  *
407  * Request for TI_SCI_MSG_WRITE_SWREV
408  */
409 struct ti_sci_msq_req_set_swrev {
410 	struct ti_sci_msg_hdr hdr;
411 	uint8_t identifier;
412 	uint32_t swrev;
413 } __packed;
414 
415 /**
416  * struct ti_sci_msq_resp_set_swrev - Response for writing the Software Revision
417  * in OTP
418  * @hdr:	Generic header
419  *
420  * Response for TI_SCI_MSG_WRITE_SWREV
421  */
422 struct ti_sci_msq_resp_set_swrev {
423 	struct ti_sci_msg_hdr hdr;
424 } __packed;
425 
426 /**
427  * struct ti_sci_msq_req_get_swrev - Request for reading the Software Revision
428  * in OTP
429  * @hdr:	Generic header
430  * @identifier: One of the entries from enum tisci_otp_revision_identifier
431  *		(Current support only for OTP_REV_ID_SEC_BRDCFG)
432  *
433  * Request for TI_SCI_MSG_READ_SWREV
434  */
435 struct ti_sci_msq_req_get_swrev {
436 	struct ti_sci_msg_hdr hdr;
437 	uint8_t identifier;
438 } __packed;
439 
440 /**
441  * struct ti_sci_msq_resp_get_swrev - Response for reading the Software Revision
442  * in OTP
443  * @hdr:	Generic header
444  * @swrev:	Decoded Sofrware Revision value from efuses
445  *
446  * Response for TI_SCI_MSG_READ_SWREV
447  */
448 struct ti_sci_msq_resp_get_swrev {
449 	struct ti_sci_msg_hdr hdr;
450 	uint32_t swrev;
451 } __packed;
452 
453 /**
454  * struct ti_sci_msq_req_get_keycnt_keyrev - Request for reading the Key Count
455  * and Key Revision in OTP
456  * @hdr:	Generic header
457  *
458  * Request for TI_SCI_MSG_READ_KEYCNT_KEYREV
459  */
460 struct ti_sci_msq_req_get_keycnt_keyrev {
461 	struct ti_sci_msg_hdr hdr;
462 } __packed;
463 
464 /**
465  * struct ti_sci_msq_resp_get_keycnt_keyrev - Response for reading the Key Count
466  * and Key Revision in OTP
467  * Revision in OTP
468  * @hdr:	Generic header
469  * @keycnt:	Key Count integer value
470  * @keyrev:	Key Revision integer value
471  *
472  * Response for TI_SCI_MSG_READ_KEYCNT_KEYREV
473  */
474 struct ti_sci_msq_resp_get_keycnt_keyrev {
475 	struct ti_sci_msg_hdr hdr;
476 	uint32_t keycnt;
477 	uint32_t keyrev;
478 } __packed;
479 
480 /**
481  * struct ti_sci_msq_req_set_keyrev - Request for writing the Key Revision
482  * in OTP
483  * @hdr:		Generic header
484  * @value:		Key Revision value to be written
485  * @cert_addr_lo:	Lower 32 bit address of the dual signed certificate
486  * @cert_addr_hi:	Higher 32 bit address of the dual signed certificate
487  *
488  * Request for TI_SCI_MSG_WRITE_KEYREV
489  */
490 struct ti_sci_msq_req_set_keyrev {
491 	struct ti_sci_msg_hdr hdr;
492 	uint32_t value;
493 	uint32_t cert_addr_lo;
494 	uint32_t cert_addr_hi;
495 } __packed;
496 
497 /**
498  * struct ti_sci_msq_resp_set_keyrev - Response for writing the Key Revision
499  * in OTP
500  * @hdr:	Generic header
501  *
502  * Response for TI_SCI_MSG_WRITE_KEYREV
503  */
504 struct ti_sci_msq_resp_set_keyrev {
505 	struct ti_sci_msg_hdr hdr;
506 } __packed;
507 
508 #endif
509