xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision d408db99ed4c976d2cf52cfd394f8ef93073a8bc) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8
9mx6ull-flavorlist = \
10	mx6ullevk \
11	mx6ulzevk \
12
13mx6q-flavorlist = \
14	mx6qsabrelite \
15	mx6qsabreauto \
16	mx6qsabresd \
17	mx6qhmbedge \
18	mx6qapalis \
19
20mx6qp-flavorlist = \
21	mx6qpsabreauto \
22	mx6qpsabresd \
23
24mx6sl-flavorlist = \
25	mx6slevk
26
27mx6sll-flavorlist = \
28	mx6sllevk
29
30mx6sx-flavorlist = \
31	mx6sxsabreauto \
32	mx6sxsabresd \
33	mx6sxudooneofull \
34
35mx6d-flavorlist = \
36	mx6dhmbedge \
37	mx6dapalis \
38
39mx6dl-flavorlist = \
40	mx6dlsabreauto \
41	mx6dlsabresd \
42	mx6dlhmbedge \
43
44mx6s-flavorlist = \
45	mx6shmbedge \
46	mx6solosabresd \
47	mx6solosabreauto \
48
49mx7d-flavorlist = \
50	mx7dsabresd \
51	mx7dpico_mbl \
52	mx7dclsom \
53
54mx7s-flavorlist = \
55	mx7swarp7 \
56	mx7swarp7_mbl \
57
58mx7ulp-flavorlist = \
59	mx7ulpevk
60
61mx8mq-flavorlist = \
62	mx8mqevk
63
64mx8mm-flavorlist = \
65	mx8mmevk
66
67mx8mn-flavorlist = \
68	mx8mnevk
69
70mx8qm-flavorlist = \
71	mx8qmmek \
72
73mx8qx-flavorlist = \
74	mx8qxpmek \
75
76ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
77$(call force,CFG_MX6,y)
78$(call force,CFG_MX6UL,y)
79$(call force,CFG_TEE_CORE_NB_CORE,1)
80include core/arch/arm/cpu/cortex-a7.mk
81else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
82$(call force,CFG_MX6,y)
83$(call force,CFG_MX6ULL,y)
84$(call force,CFG_TEE_CORE_NB_CORE,1)
85$(call force,CFG_IMX_CAAM,n)
86$(call force,CFG_NXP_CAAM,n)
87include core/arch/arm/cpu/cortex-a7.mk
88else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
89$(call force,CFG_MX6,y)
90$(call force,CFG_MX6Q,y)
91$(call force,CFG_TEE_CORE_NB_CORE,4)
92else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
93$(call force,CFG_MX6,y)
94$(call force,CFG_MX6QP,y)
95$(call force,CFG_TEE_CORE_NB_CORE,4)
96else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
97$(call force,CFG_MX6,y)
98$(call force,CFG_MX6D,y)
99$(call force,CFG_TEE_CORE_NB_CORE,2)
100else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
101$(call force,CFG_MX6,y)
102$(call force,CFG_MX6DL,y)
103$(call force,CFG_TEE_CORE_NB_CORE,2)
104else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
105$(call force,CFG_MX6,y)
106$(call force,CFG_MX6S,y)
107$(call force,CFG_TEE_CORE_NB_CORE,1)
108else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
109$(call force,CFG_MX6,y)
110$(call force,CFG_MX6SL,y)
111$(call force,CFG_TEE_CORE_NB_CORE,1)
112$(call force,CFG_IMX_CAAM,n)
113$(call force,CFG_NXP_CAAM,n)
114else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
115$(call force,CFG_MX6,y)
116$(call force,CFG_MX6SLL,y)
117$(call force,CFG_TEE_CORE_NB_CORE,1)
118$(call force,CFG_IMX_CAAM,n)
119$(call force,CFG_NXP_CAAM,n)
120else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
121$(call force,CFG_MX6,y)
122$(call force,CFG_MX6SX,y)
123$(call force,CFG_TEE_CORE_NB_CORE,1)
124else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
125$(call force,CFG_MX7,y)
126$(call force,CFG_TEE_CORE_NB_CORE,1)
127include core/arch/arm/cpu/cortex-a7.mk
128else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
129$(call force,CFG_MX7,y)
130$(call force,CFG_TEE_CORE_NB_CORE,2)
131include core/arch/arm/cpu/cortex-a7.mk
132else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
133$(call force,CFG_MX7ULP,y)
134$(call force,CFG_TEE_CORE_NB_CORE,1)
135$(call force,CFG_TZC380,n)
136$(call force,CFG_CSU,n)
137$(call force,CFG_NXP_CAAM,n)
138include core/arch/arm/cpu/cortex-a7.mk
139else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
140$(call force,CFG_MX8MQ,y)
141$(call force,CFG_ARM64_core,y)
142CFG_IMX_UART ?= y
143CFG_DRAM_BASE ?= 0x40000000
144CFG_TEE_CORE_NB_CORE ?= 4
145else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
146$(call force,CFG_MX8MM,y)
147$(call force,CFG_ARM64_core,y)
148CFG_IMX_UART ?= y
149CFG_DRAM_BASE ?= 0x40000000
150CFG_TEE_CORE_NB_CORE ?= 4
151else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
152$(call force,CFG_MX8MN,y)
153$(call force,CFG_ARM64_core,y)
154CFG_IMX_UART ?= y
155CFG_DRAM_BASE ?= 0x40000000
156CFG_TEE_CORE_NB_CORE ?= 4
157else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
158$(call force,CFG_MX8QM,y)
159$(call force,CFG_ARM64_core,y)
160$(call force,CFG_IMX_SNVS,n)
161CFG_IMX_LPUART ?= y
162CFG_DRAM_BASE ?= 0x80000000
163CFG_TEE_CORE_NB_CORE ?= 6
164$(call force,CFG_NXP_CAAM,n)
165else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
166$(call force,CFG_MX8QX,y)
167$(call force,CFG_ARM64_core,y)
168CFG_IMX_LPUART ?= y
169CFG_DRAM_BASE ?= 0x80000000
170CFG_TEE_CORE_NB_CORE ?= 4
171$(call force,CFG_NXP_CAAM,n)
172else
173$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
174endif
175
176ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
177CFG_DDR_SIZE ?= 0x40000000
178CFG_NS_ENTRY_ADDR ?= 0x80800000
179endif
180
181ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
182CFG_DDR_SIZE ?= 0x40000000
183CFG_UART_BASE ?= UART1_BASE
184endif
185
186ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
187CFG_DDR_SIZE ?= 0x20000000
188CFG_NS_ENTRY_ADDR ?= 0x87800000
189CFG_DT_ADDR ?= 0x83100000
190CFG_UART_BASE ?= UART5_BASE
191CFG_BOOT_SECONDARY_REQUEST ?= n
192CFG_EXTERNAL_DTB_OVERLAY ?= y
193CFG_IMX_WDOG_EXT_RESET ?= y
194endif
195
196ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
197CFG_DDR_SIZE ?= 0x20000000
198CFG_NS_ENTRY_ADDR ?= 0x80800000
199CFG_BOOT_SECONDARY_REQUEST ?= n
200endif
201
202ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
203CFG_DDR_SIZE ?= 0x20000000
204CFG_NS_ENTRY_ADDR ?= 0x87800000
205CFG_DT_ADDR ?= 0x83100000
206CFG_BOOT_SECONDARY_REQUEST ?= n
207CFG_EXTERNAL_DTB_OVERLAY = y
208CFG_IMX_WDOG_EXT_RESET = y
209endif
210
211ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
212CFG_DDR_SIZE ?= 0x40000000
213CFG_NS_ENTRY_ADDR ?= 0x60800000
214CFG_UART_BASE ?= UART4_BASE
215endif
216
217ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
218	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
219	mx6dapalis mx6qapalis))
220CFG_DDR_SIZE ?= 0x40000000
221CFG_NS_ENTRY_ADDR ?= 0x12000000
222endif
223
224ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
225	mx6dlsabreauto mx6solosabreauto))
226CFG_DDR_SIZE ?= 0x80000000
227CFG_NS_ENTRY_ADDR ?= 0x12000000
228CFG_UART_BASE ?= UART4_BASE
229endif
230
231ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
232CFG_DDR_SIZE ?= 0x80000000
233CFG_UART_BASE ?= UART1_BASE
234endif
235
236ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
237CFG_DDR_SIZE ?= 0x40000000
238CFG_NS_ENTRY_ADDR ?= 0x12000000
239endif
240
241ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
242CFG_DDR_SIZE ?= 0x40000000
243CFG_NS_ENTRY_ADDR ?= 0x12000000
244CFG_UART_BASE ?= UART2_BASE
245endif
246
247ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
248CFG_NS_ENTRY_ADDR ?= 0x80800000
249CFG_DDR_SIZE ?= 0x40000000
250endif
251
252ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
253CFG_NS_ENTRY_ADDR ?= 0x80800000
254CFG_DDR_SIZE ?= 0x80000000
255endif
256
257ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
258CFG_DDR_SIZE ?= 0x80000000
259CFG_NS_ENTRY_ADDR ?= 0x80800000
260endif
261
262ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
263CFG_DDR_SIZE ?= 0x40000000
264CFG_NS_ENTRY_ADDR ?= 0x80800000
265endif
266
267ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
268CFG_DDR_SIZE ?= 0x40000000
269CFG_UART_BASE ?= UART1_BASE
270endif
271
272ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
273CFG_DDR_SIZE ?= 0x20000000
274CFG_NS_ENTRY_ADDR ?= 0x80800000
275endif
276
277ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
278CFG_DDR_SIZE ?= 0x10000000
279CFG_NS_ENTRY_ADDR ?= 0x80800000
280CFG_UART_BASE ?= UART5_BASE
281endif
282
283ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
284CFG_DDR_SIZE ?= 0x10000000
285CFG_NS_ENTRY_ADDR ?= 0x80800000
286endif
287
288ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
289CFG_DDR_SIZE ?= 0xc0000000
290CFG_UART_BASE ?= UART1_BASE
291endif
292
293ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
294CFG_DDR_SIZE ?= 0x80000000
295CFG_UART_BASE ?= UART2_BASE
296endif
297
298ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
299CFG_DDR_SIZE ?= 0x80000000
300CFG_UART_BASE ?= UART2_BASE
301endif
302
303ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
304CFG_DDR_SIZE ?= 0x80000000
305CFG_UART_BASE ?= UART0_BASE
306endif
307
308# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
309ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
310	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
311include core/arch/arm/cpu/cortex-a9.mk
312
313$(call force,CFG_PL310,y)
314
315CFG_PL310_LOCKED ?= y
316CFG_ENABLE_SCTLR_RR ?= y
317CFG_SCU ?= y
318endif
319
320ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
321CFG_DRAM_BASE ?= 0x10000000
322endif
323
324ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
325	$(CFG_MX6SX)))
326CFG_DRAM_BASE ?= 0x80000000
327endif
328
329ifeq ($(filter y, $(CFG_MX7)), y)
330CFG_INIT_CNTVOFF ?= y
331CFG_DRAM_BASE ?= 0x80000000
332endif
333
334ifeq ($(filter y, $(CFG_MX7ULP)), y)
335CFG_INIT_CNTVOFF ?= y
336CFG_DRAM_BASE ?= UL(0x60000000)
337$(call force,CFG_IMX_LPUART,y)
338$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
339endif
340
341ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
342$(call force,CFG_GENERIC_BOOT,y)
343$(call force,CFG_GIC,y)
344$(call force,CFG_PM_STUBS,y)
345
346CFG_BOOT_SYNC_CPU ?= n
347CFG_BOOT_SECONDARY_REQUEST ?= y
348CFG_DT ?= y
349CFG_PAGEABLE_ADDR ?= 0
350CFG_PSCI_ARM32 ?= y
351CFG_SECURE_TIME_SOURCE_REE ?= y
352CFG_UART_BASE ?= UART1_BASE
353endif
354
355ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
356$(call force,CFG_IMX_UART,y)
357CFG_CSU ?= y
358endif
359
360ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
361CFG_HWSUPP_MEM_PERM_WXN = n
362CFG_IMX_WDOG ?= y
363endif
364
365ifeq ($(CFG_ARM64_core),y)
366# arm-v8 platforms
367include core/arch/arm/cpu/cortex-armv8-0.mk
368$(call force,CFG_ARM_GICV3,y)
369$(call force,CFG_GENERIC_BOOT,y)
370$(call force,CFG_GIC,y)
371$(call force,CFG_WITH_LPAE,y)
372$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
373$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
374
375CFG_CRYPTO_WITH_CE ?= y
376CFG_PM_STUBS ?= y
377
378supported-ta-targets = ta_arm64
379endif
380
381CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - 0x02000000 + $(CFG_DDR_SIZE))
382CFG_TZDRAM_SIZE ?= 0x01e00000
383CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
384CFG_SHMEM_SIZE ?= 0x00200000
385
386CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
387CFG_WITH_STACK_CANARIES ?= y
388CFG_MMAP_REGIONS ?= 24
389
390# Almost all platforms include CAAM HW Modules, except the
391# ones forced to be disabled
392CFG_NXP_CAAM ?= n
393
394ifeq ($(CFG_NXP_CAAM),y)
395# As NXP CAAM Driver is enabled, disable the small local CAAM driver
396# used just to release Job Rings to Non-Secure world
397$(call force,CFG_IMX_CAAM,n)
398
399# If NXP CAAM Driver is supported, the Crypto Driver interfacing
400# it with generic crypto API can be enabled.
401CFG_CRYPTO_DRIVER ?= y
402# Crypto Driver Debug
403CFG_CRYPTO_DRIVER_DEBUG ?= n
404else
405$(call force,CFG_CRYPTO_DRIVER,n)
406$(call force,CFG_WITH_SOFTWARE_PRNG,y)
407
408ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
409CFG_IMX_CAAM ?= y
410endif
411endif
412
413# Cryptographic configuration
414include core/arch/arm/plat-imx/crypto_conf.mk
415