xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision c54ad22aaecb6c52bdb8abb41cd0b11279f6fecd) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate
68
69mx8mn-flavorlist = \
70	mx8mnevk
71
72mx8mp-flavorlist = \
73	mx8mpevk \
74	mx8mp_rsb3720_6g
75
76mx8qm-flavorlist = \
77	mx8qmmek \
78
79mx8qx-flavorlist = \
80	mx8qxpmek \
81
82ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
83$(call force,CFG_MX6,y)
84$(call force,CFG_MX6UL,y)
85$(call force,CFG_TEE_CORE_NB_CORE,1)
86$(call force,CFG_TZC380,y)
87include core/arch/arm/cpu/cortex-a7.mk
88else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
89$(call force,CFG_MX6,y)
90$(call force,CFG_MX6ULL,y)
91$(call force,CFG_TEE_CORE_NB_CORE,1)
92$(call force,CFG_TZC380,y)
93$(call force,CFG_IMX_CAAM,n)
94$(call force,CFG_NXP_CAAM,n)
95$(call force,CFG_IMX_DCP,y)
96include core/arch/arm/cpu/cortex-a7.mk
97else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
98$(call force,CFG_MX6,y)
99$(call force,CFG_MX6Q,y)
100$(call force,CFG_TEE_CORE_NB_CORE,4)
101$(call force,CFG_TZC380,y)
102else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
103$(call force,CFG_MX6,y)
104$(call force,CFG_MX6QP,y)
105$(call force,CFG_TEE_CORE_NB_CORE,4)
106else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
107$(call force,CFG_MX6,y)
108$(call force,CFG_MX6D,y)
109$(call force,CFG_TEE_CORE_NB_CORE,2)
110$(call force,CFG_TZC380,y)
111else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
112$(call force,CFG_MX6,y)
113$(call force,CFG_MX6DL,y)
114$(call force,CFG_TEE_CORE_NB_CORE,2)
115$(call force,CFG_TZC380,y)
116else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
117$(call force,CFG_MX6,y)
118$(call force,CFG_MX6S,y)
119$(call force,CFG_TEE_CORE_NB_CORE,1)
120else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
121$(call force,CFG_MX6,y)
122$(call force,CFG_MX6SL,y)
123$(call force,CFG_TEE_CORE_NB_CORE,1)
124$(call force,CFG_IMX_CAAM,n)
125$(call force,CFG_NXP_CAAM,n)
126$(call force,CFG_IMX_DCP,y)
127else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
128$(call force,CFG_MX6,y)
129$(call force,CFG_MX6SLL,y)
130$(call force,CFG_TEE_CORE_NB_CORE,1)
131$(call force,CFG_IMX_CAAM,n)
132$(call force,CFG_NXP_CAAM,n)
133$(call force,CFG_IMX_DCP,y)
134$(call force,CFG_NO_SMP,y)
135else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
136$(call force,CFG_MX6,y)
137$(call force,CFG_MX6SX,y)
138$(call force,CFG_TEE_CORE_NB_CORE,1)
139else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
140$(call force,CFG_MX7,y)
141$(call force,CFG_TEE_CORE_NB_CORE,1)
142include core/arch/arm/cpu/cortex-a7.mk
143else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
144$(call force,CFG_MX7,y)
145$(call force,CFG_TEE_CORE_NB_CORE,2)
146include core/arch/arm/cpu/cortex-a7.mk
147else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
148$(call force,CFG_MX7ULP,y)
149$(call force,CFG_TEE_CORE_NB_CORE,1)
150$(call force,CFG_TZC380,n)
151$(call force,CFG_CSU,n)
152$(call force,CFG_NXP_CAAM,n)
153include core/arch/arm/cpu/cortex-a7.mk
154else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
155$(call force,CFG_MX8MQ,y)
156$(call force,CFG_MX8M,y)
157$(call force,CFG_ARM64_core,y)
158CFG_IMX_UART ?= y
159CFG_DRAM_BASE ?= 0x40000000
160CFG_TEE_CORE_NB_CORE ?= 4
161else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
162$(call force,CFG_MX8MM,y)
163$(call force,CFG_MX8M,y)
164$(call force,CFG_ARM64_core,y)
165CFG_IMX_UART ?= y
166CFG_DRAM_BASE ?= 0x40000000
167CFG_TEE_CORE_NB_CORE ?= 4
168else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
169$(call force,CFG_MX8MN,y)
170$(call force,CFG_MX8M,y)
171$(call force,CFG_ARM64_core,y)
172CFG_IMX_UART ?= y
173CFG_DRAM_BASE ?= 0x40000000
174CFG_TEE_CORE_NB_CORE ?= 4
175else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
176$(call force,CFG_MX8MP,y)
177$(call force,CFG_MX8M,y)
178$(call force,CFG_ARM64_core,y)
179CFG_IMX_UART ?= y
180CFG_DRAM_BASE ?= 0x40000000
181CFG_TEE_CORE_NB_CORE ?= 4
182else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
183$(call force,CFG_MX8QM,y)
184$(call force,CFG_ARM64_core,y)
185$(call force,CFG_IMX_SNVS,n)
186CFG_IMX_LPUART ?= y
187CFG_DRAM_BASE ?= 0x80000000
188CFG_TEE_CORE_NB_CORE ?= 6
189$(call force,CFG_IMX_OCOTP,n)
190else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
191$(call force,CFG_MX8QX,y)
192$(call force,CFG_ARM64_core,y)
193$(call force,CFG_IMX_SNVS,n)
194CFG_IMX_LPUART ?= y
195CFG_DRAM_BASE ?= 0x80000000
196CFG_TEE_CORE_NB_CORE ?= 4
197$(call force,CFG_IMX_OCOTP,n)
198else
199$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
200endif
201
202ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
203CFG_DDR_SIZE ?= 0x40000000
204CFG_NS_ENTRY_ADDR ?= 0x80800000
205endif
206
207ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
208CFG_DDR_SIZE ?= 0x40000000
209CFG_UART_BASE ?= UART1_BASE
210endif
211
212ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
213CFG_DDR_SIZE ?= 0x20000000
214CFG_NS_ENTRY_ADDR ?= 0x87800000
215CFG_DT_ADDR ?= 0x83100000
216CFG_UART_BASE ?= UART5_BASE
217CFG_BOOT_SECONDARY_REQUEST ?= n
218CFG_EXTERNAL_DTB_OVERLAY ?= y
219CFG_IMX_WDOG_EXT_RESET ?= y
220endif
221
222ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
223CFG_DDR_SIZE ?= 0x20000000
224CFG_NS_ENTRY_ADDR ?= 0x80800000
225CFG_BOOT_SECONDARY_REQUEST ?= n
226endif
227
228ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
229CFG_DDR_SIZE ?= 0x20000000
230CFG_NS_ENTRY_ADDR ?= 0x87800000
231CFG_DT_ADDR ?= 0x83100000
232CFG_BOOT_SECONDARY_REQUEST ?= n
233CFG_EXTERNAL_DTB_OVERLAY = y
234CFG_IMX_WDOG_EXT_RESET = y
235endif
236
237ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
238CFG_DDR_SIZE ?= 0x40000000
239CFG_NS_ENTRY_ADDR ?= 0x60800000
240CFG_UART_BASE ?= UART4_BASE
241endif
242
243ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
244	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
245	mx6dapalis mx6qapalis))
246CFG_DDR_SIZE ?= 0x40000000
247CFG_NS_ENTRY_ADDR ?= 0x12000000
248endif
249
250ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
251	mx6dlsabreauto mx6solosabreauto))
252CFG_DDR_SIZE ?= 0x80000000
253CFG_NS_ENTRY_ADDR ?= 0x12000000
254CFG_UART_BASE ?= UART4_BASE
255endif
256
257ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
258CFG_DDR_SIZE ?= 0x80000000
259CFG_UART_BASE ?= UART1_BASE
260endif
261
262ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
263CFG_DDR_SIZE ?= 0x40000000
264CFG_NS_ENTRY_ADDR ?= 0x12000000
265endif
266
267ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
268CFG_DDR_SIZE ?= 0x40000000
269CFG_NS_ENTRY_ADDR ?= 0x12000000
270CFG_UART_BASE ?= UART2_BASE
271endif
272
273ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
274CFG_NS_ENTRY_ADDR ?= 0x80800000
275CFG_DDR_SIZE ?= 0x40000000
276endif
277
278ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
279CFG_NS_ENTRY_ADDR ?= 0x80800000
280CFG_DDR_SIZE ?= 0x80000000
281endif
282
283ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
284CFG_DDR_SIZE ?= 0x80000000
285CFG_NS_ENTRY_ADDR ?= 0x80800000
286endif
287
288ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
289CFG_DDR_SIZE ?= 0x40000000
290CFG_NS_ENTRY_ADDR ?= 0x80800000
291endif
292
293ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
294CFG_DDR_SIZE ?= 0x40000000
295CFG_UART_BASE ?= UART1_BASE
296endif
297
298ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
299CFG_DDR_SIZE ?= 0x20000000
300CFG_NS_ENTRY_ADDR ?= 0x80800000
301endif
302
303ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
304CFG_DDR_SIZE ?= 0x10000000
305CFG_NS_ENTRY_ADDR ?= 0x80800000
306CFG_UART_BASE ?= UART5_BASE
307endif
308
309ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
310CFG_DDR_SIZE ?= 0x10000000
311CFG_NS_ENTRY_ADDR ?= 0x80800000
312endif
313
314ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
315CFG_DDR_SIZE ?= 0x10000000
316CFG_UART_BASE ?= UART7_BASE
317endif
318
319ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
320CFG_DDR_SIZE ?= 0xc0000000
321CFG_UART_BASE ?= UART1_BASE
322endif
323
324ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
325CFG_DDR_SIZE ?= 0x80000000
326CFG_UART_BASE ?= UART2_BASE
327endif
328
329ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
330CFG_DDR_SIZE ?= 0x40000000
331CFG_UART_BASE ?= UART3_BASE
332CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
333CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
334endif
335
336ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
337CFG_DDR_SIZE ?= 0x80000000
338CFG_UART_BASE ?= UART2_BASE
339endif
340
341ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
342CFG_DDR_SIZE ?= UL(0x180000000)
343CFG_UART_BASE ?= UART2_BASE
344$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
345$(call force,CFG_CORE_ARM64_PA_BITS,36)
346endif
347
348ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
349CFG_DDR_SIZE ?= UL(0x180000000)
350CFG_UART_BASE ?= UART3_BASE
351CFG_TZDRAM_START ?= 0x56000000
352$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
353$(call force,CFG_CORE_ARM64_PA_BITS,36)
354endif
355
356ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
357CFG_DDR_SIZE ?= 0x80000000
358CFG_UART_BASE ?= UART0_BASE
359CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
360CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
361CFG_CORE_ARM64_PA_BITS ?= 40
362endif
363
364# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
365ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
366	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
367include core/arch/arm/cpu/cortex-a9.mk
368
369$(call force,CFG_PL310,y)
370
371CFG_PL310_LOCKED ?= y
372CFG_ENABLE_SCTLR_RR ?= y
373CFG_SCU ?= y
374endif
375
376ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
377CFG_DRAM_BASE ?= 0x10000000
378endif
379
380ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
381	$(CFG_MX6SX)))
382CFG_DRAM_BASE ?= 0x80000000
383endif
384
385ifeq ($(filter y, $(CFG_MX7)), y)
386CFG_INIT_CNTVOFF ?= y
387CFG_DRAM_BASE ?= 0x80000000
388endif
389
390ifeq ($(filter y, $(CFG_MX7ULP)), y)
391CFG_INIT_CNTVOFF ?= y
392CFG_DRAM_BASE ?= UL(0x60000000)
393$(call force,CFG_IMX_LPUART,y)
394$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
395endif
396
397ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
398$(call force,CFG_GIC,y)
399
400CFG_BOOT_SECONDARY_REQUEST ?= y
401CFG_DT ?= y
402CFG_DTB_MAX_SIZE ?= 0x20000
403CFG_PAGEABLE_ADDR ?= 0
404CFG_PSCI_ARM32 ?= y
405CFG_SECURE_TIME_SOURCE_REE ?= y
406CFG_UART_BASE ?= UART1_BASE
407endif
408
409ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8MM)))
410$(call force,CFG_IMX_UART,y)
411ifeq ($(CFG_RPMB_FS),y)
412CFG_IMX_SNVS ?= y
413endif
414endif
415
416ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
417CFG_CSU ?= y
418endif
419
420ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
421CFG_HWSUPP_MEM_PERM_WXN = n
422CFG_IMX_WDOG ?= y
423endif
424
425ifeq ($(CFG_ARM64_core),y)
426# arm-v8 platforms
427include core/arch/arm/cpu/cortex-armv8-0.mk
428$(call force,CFG_ARM_GICV3,y)
429$(call force,CFG_GIC,y)
430$(call force,CFG_WITH_LPAE,y)
431$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
432$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
433
434CFG_CRYPTO_WITH_CE ?= y
435
436supported-ta-targets = ta_arm64
437endif
438
439CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - 0x02000000 + $(CFG_DDR_SIZE))
440CFG_TZDRAM_SIZE ?= 0x01e00000
441CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
442CFG_SHMEM_SIZE ?= 0x00200000
443
444CFG_NSEC_DDR_0_BASE ?= $(CFG_DRAM_BASE)
445CFG_NSEC_DDR_0_SIZE ?= ($(CFG_DDR_SIZE) - 0x02000000)
446
447CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
448CFG_MMAP_REGIONS ?= 24
449
450# SE05X and OCOTP both implement tee_otp_get_die_id()
451ifeq ($(CFG_NXP_SE05X),y)
452$(call force,CFG_IMX_OCOTP,n)
453endif
454CFG_IMX_OCOTP ?= y
455
456# Almost all platforms include CAAM HW Modules, except the
457# ones forced to be disabled
458CFG_NXP_CAAM ?= n
459
460ifeq ($(CFG_NXP_CAAM),y)
461ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX)), y)
462CFG_IMX_SC ?= y
463endif
464
465# As NXP CAAM Driver is enabled, disable the small local CAAM driver
466# used just to release Job Rings to Non-Secure world
467$(call force,CFG_IMX_CAAM,n)
468else
469
470ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
471CFG_IMX_CAAM ?= y
472endif
473endif
474
475# Cryptographic configuration
476include core/arch/arm/plat-imx/crypto_conf.mk
477