xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision c44d734b6366cbf4d12610310e809872db65f89d) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate
68
69mx8mn-flavorlist = \
70	mx8mnevk
71
72mx8mp-flavorlist = \
73	mx8mpevk \
74	mx8mp_rsb3720_6g
75
76mx8qm-flavorlist = \
77	mx8qmmek \
78
79mx8qx-flavorlist = \
80	mx8qxpmek \
81
82mx8dxl-flavorlist = \
83	mx8dxlevk \
84
85mx8ulp-flavorlist = \
86	mx8ulpevk \
87
88ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
89$(call force,CFG_MX6,y)
90$(call force,CFG_MX6UL,y)
91$(call force,CFG_TEE_CORE_NB_CORE,1)
92$(call force,CFG_TZC380,y)
93include core/arch/arm/cpu/cortex-a7.mk
94else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
95$(call force,CFG_MX6,y)
96$(call force,CFG_MX6ULL,y)
97$(call force,CFG_TEE_CORE_NB_CORE,1)
98$(call force,CFG_TZC380,y)
99$(call force,CFG_IMX_CAAM,n)
100$(call force,CFG_NXP_CAAM,n)
101$(call force,CFG_IMX_DCP,y)
102include core/arch/arm/cpu/cortex-a7.mk
103else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
104$(call force,CFG_MX6,y)
105$(call force,CFG_MX6Q,y)
106$(call force,CFG_TEE_CORE_NB_CORE,4)
107$(call force,CFG_TZC380,y)
108else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
109$(call force,CFG_MX6,y)
110$(call force,CFG_MX6QP,y)
111$(call force,CFG_TEE_CORE_NB_CORE,4)
112else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
113$(call force,CFG_MX6,y)
114$(call force,CFG_MX6D,y)
115$(call force,CFG_TEE_CORE_NB_CORE,2)
116$(call force,CFG_TZC380,y)
117else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
118$(call force,CFG_MX6,y)
119$(call force,CFG_MX6DL,y)
120$(call force,CFG_TEE_CORE_NB_CORE,2)
121$(call force,CFG_TZC380,y)
122else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
123$(call force,CFG_MX6,y)
124$(call force,CFG_MX6S,y)
125$(call force,CFG_TEE_CORE_NB_CORE,1)
126else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
127$(call force,CFG_MX6,y)
128$(call force,CFG_MX6SL,y)
129$(call force,CFG_TEE_CORE_NB_CORE,1)
130$(call force,CFG_IMX_CAAM,n)
131$(call force,CFG_NXP_CAAM,n)
132$(call force,CFG_IMX_DCP,y)
133else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
134$(call force,CFG_MX6,y)
135$(call force,CFG_MX6SLL,y)
136$(call force,CFG_TEE_CORE_NB_CORE,1)
137$(call force,CFG_IMX_CAAM,n)
138$(call force,CFG_NXP_CAAM,n)
139$(call force,CFG_IMX_DCP,y)
140$(call force,CFG_NO_SMP,y)
141else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
142$(call force,CFG_MX6,y)
143$(call force,CFG_MX6SX,y)
144$(call force,CFG_TEE_CORE_NB_CORE,1)
145else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
146$(call force,CFG_MX7,y)
147$(call force,CFG_TEE_CORE_NB_CORE,1)
148include core/arch/arm/cpu/cortex-a7.mk
149else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
150$(call force,CFG_MX7,y)
151$(call force,CFG_TEE_CORE_NB_CORE,2)
152include core/arch/arm/cpu/cortex-a7.mk
153else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
154$(call force,CFG_MX7ULP,y)
155$(call force,CFG_TEE_CORE_NB_CORE,1)
156$(call force,CFG_TZC380,n)
157$(call force,CFG_CSU,n)
158$(call force,CFG_NXP_CAAM,n)
159include core/arch/arm/cpu/cortex-a7.mk
160else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
161$(call force,CFG_MX8MQ,y)
162$(call force,CFG_MX8M,y)
163$(call force,CFG_ARM64_core,y)
164CFG_DRAM_BASE ?= 0x40000000
165CFG_TEE_CORE_NB_CORE ?= 4
166else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
167$(call force,CFG_MX8MM,y)
168$(call force,CFG_MX8M,y)
169$(call force,CFG_ARM64_core,y)
170CFG_DRAM_BASE ?= 0x40000000
171CFG_TEE_CORE_NB_CORE ?= 4
172else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
173$(call force,CFG_MX8MN,y)
174$(call force,CFG_MX8M,y)
175$(call force,CFG_ARM64_core,y)
176CFG_DRAM_BASE ?= 0x40000000
177CFG_TEE_CORE_NB_CORE ?= 4
178else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
179$(call force,CFG_MX8MP,y)
180$(call force,CFG_MX8M,y)
181$(call force,CFG_ARM64_core,y)
182CFG_DRAM_BASE ?= 0x40000000
183CFG_TEE_CORE_NB_CORE ?= 4
184else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
185$(call force,CFG_MX8QM,y)
186$(call force,CFG_ARM64_core,y)
187$(call force,CFG_IMX_SNVS,n)
188CFG_IMX_LPUART ?= y
189CFG_DRAM_BASE ?= 0x80000000
190CFG_TEE_CORE_NB_CORE ?= 6
191$(call force,CFG_IMX_OCOTP,n)
192else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
193$(call force,CFG_MX8QX,y)
194$(call force,CFG_ARM64_core,y)
195$(call force,CFG_IMX_SNVS,n)
196CFG_IMX_LPUART ?= y
197CFG_DRAM_BASE ?= 0x80000000
198CFG_TEE_CORE_NB_CORE ?= 4
199$(call force,CFG_IMX_OCOTP,n)
200else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
201$(call force,CFG_MX8DXL,y)
202$(call force,CFG_ARM64_core,y)
203$(call force,CFG_IMX_SNVS,n)
204CFG_IMX_LPUART ?= y
205CFG_DRAM_BASE ?= 0x80000000
206$(call force,CFG_TEE_CORE_NB_CORE,2)
207$(call force,CFG_IMX_OCOTP,n)
208$(call force,CFG_NXP_CAAM,n)
209else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist)))
210$(call force,CFG_MX8ULP,y)
211$(call force,CFG_ARM64_core,y)
212CFG_IMX_LPUART ?= y
213CFG_DRAM_BASE ?= 0x80000000
214CFG_TEE_CORE_NB_CORE ?= 2
215$(call force,CFG_NXP_SNVS,n)
216$(call force,CFG_IMX_OCOTP,n)
217else
218$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
219endif
220
221ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
222CFG_DDR_SIZE ?= 0x40000000
223CFG_NS_ENTRY_ADDR ?= 0x80800000
224CFG_IMX_WDOG_EXT_RESET ?= y
225endif
226
227ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
228CFG_DDR_SIZE ?= 0x40000000
229CFG_UART_BASE ?= UART1_BASE
230CFG_IMX_WDOG_EXT_RESET ?= y
231endif
232
233ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
234CFG_DDR_SIZE ?= 0x20000000
235CFG_NS_ENTRY_ADDR ?= 0x87800000
236CFG_DT_ADDR ?= 0x83100000
237CFG_UART_BASE ?= UART5_BASE
238CFG_BOOT_SECONDARY_REQUEST ?= n
239CFG_EXTERNAL_DTB_OVERLAY ?= y
240CFG_IMX_WDOG_EXT_RESET ?= y
241endif
242
243ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
244CFG_DDR_SIZE ?= 0x20000000
245CFG_NS_ENTRY_ADDR ?= 0x80800000
246CFG_BOOT_SECONDARY_REQUEST ?= n
247endif
248
249ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
250CFG_DDR_SIZE ?= 0x20000000
251CFG_NS_ENTRY_ADDR ?= 0x87800000
252CFG_DT_ADDR ?= 0x83100000
253CFG_BOOT_SECONDARY_REQUEST ?= n
254CFG_EXTERNAL_DTB_OVERLAY = y
255CFG_IMX_WDOG_EXT_RESET = y
256endif
257
258ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
259CFG_DDR_SIZE ?= 0x40000000
260CFG_NS_ENTRY_ADDR ?= 0x60800000
261CFG_UART_BASE ?= UART4_BASE
262endif
263
264ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
265	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
266	mx6dapalis mx6qapalis))
267CFG_DDR_SIZE ?= 0x40000000
268CFG_NS_ENTRY_ADDR ?= 0x12000000
269endif
270
271ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
272	mx6dlsabreauto mx6solosabreauto))
273CFG_DDR_SIZE ?= 0x80000000
274CFG_NS_ENTRY_ADDR ?= 0x12000000
275CFG_UART_BASE ?= UART4_BASE
276endif
277
278ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
279CFG_DDR_SIZE ?= 0x80000000
280CFG_UART_BASE ?= UART1_BASE
281endif
282
283ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
284CFG_DDR_SIZE ?= 0x40000000
285CFG_NS_ENTRY_ADDR ?= 0x12000000
286endif
287
288ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
289CFG_DDR_SIZE ?= 0x40000000
290CFG_NS_ENTRY_ADDR ?= 0x12000000
291CFG_UART_BASE ?= UART2_BASE
292endif
293
294ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
295CFG_NS_ENTRY_ADDR ?= 0x80800000
296CFG_DDR_SIZE ?= 0x40000000
297endif
298
299ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
300CFG_NS_ENTRY_ADDR ?= 0x80800000
301CFG_DDR_SIZE ?= 0x80000000
302endif
303
304ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
305CFG_DDR_SIZE ?= 0x80000000
306CFG_NS_ENTRY_ADDR ?= 0x80800000
307endif
308
309ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
310CFG_DDR_SIZE ?= 0x40000000
311CFG_NS_ENTRY_ADDR ?= 0x80800000
312endif
313
314ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
315CFG_DDR_SIZE ?= 0x40000000
316CFG_UART_BASE ?= UART1_BASE
317endif
318
319ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
320CFG_DDR_SIZE ?= 0x20000000
321CFG_NS_ENTRY_ADDR ?= 0x80800000
322endif
323
324ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
325CFG_DDR_SIZE ?= 0x10000000
326CFG_NS_ENTRY_ADDR ?= 0x80800000
327CFG_UART_BASE ?= UART5_BASE
328endif
329
330ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
331CFG_DDR_SIZE ?= 0x10000000
332CFG_NS_ENTRY_ADDR ?= 0x80800000
333endif
334
335ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
336CFG_DDR_SIZE ?= 0x10000000
337CFG_UART_BASE ?= UART7_BASE
338endif
339
340ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
341CFG_DDR_SIZE ?= 0xc0000000
342CFG_UART_BASE ?= UART1_BASE
343endif
344
345ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
346CFG_DDR_SIZE ?= 0x80000000
347CFG_UART_BASE ?= UART2_BASE
348endif
349
350ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
351CFG_DDR_SIZE ?= 0x40000000
352CFG_UART_BASE ?= UART3_BASE
353CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
354CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
355endif
356
357ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
358CFG_DDR_SIZE ?= 0x80000000
359CFG_UART_BASE ?= UART2_BASE
360endif
361
362ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
363CFG_DDR_SIZE ?= UL(0x180000000)
364CFG_UART_BASE ?= UART2_BASE
365$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
366$(call force,CFG_CORE_ARM64_PA_BITS,36)
367endif
368
369ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
370CFG_DDR_SIZE ?= UL(0x180000000)
371CFG_UART_BASE ?= UART3_BASE
372CFG_TZDRAM_START ?= 0x56000000
373$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
374$(call force,CFG_CORE_ARM64_PA_BITS,36)
375endif
376
377ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
378CFG_DDR_SIZE ?= 0x80000000
379CFG_UART_BASE ?= UART0_BASE
380CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
381CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
382CFG_CORE_ARM64_PA_BITS ?= 40
383endif
384
385ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
386CFG_DDR_SIZE ?= 0x40000000
387CFG_UART_BASE ?= UART0_BASE
388endif
389
390ifneq (,$(filter $(PLATFORM_FLAVOR),mx8ulpevk))
391CFG_DDR_SIZE ?= 0x80000000
392CFG_UART_BASE ?= UART5_BASE
393endif
394
395# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
396ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
397	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
398include core/arch/arm/cpu/cortex-a9.mk
399
400$(call force,CFG_PL310,y)
401
402CFG_PL310_LOCKED ?= y
403CFG_ENABLE_SCTLR_RR ?= y
404CFG_SCU ?= y
405endif
406
407ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
408CFG_DRAM_BASE ?= 0x10000000
409endif
410
411ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
412	$(CFG_MX6SX)))
413CFG_DRAM_BASE ?= 0x80000000
414endif
415
416ifeq ($(filter y, $(CFG_MX7)), y)
417CFG_INIT_CNTVOFF ?= y
418CFG_DRAM_BASE ?= 0x80000000
419endif
420
421ifeq ($(filter y, $(CFG_MX7ULP)), y)
422CFG_INIT_CNTVOFF ?= y
423CFG_DRAM_BASE ?= UL(0x60000000)
424$(call force,CFG_IMX_LPUART,y)
425$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
426endif
427
428ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
429$(call force,CFG_GIC,y)
430
431CFG_BOOT_SECONDARY_REQUEST ?= y
432CFG_DT ?= y
433CFG_DTB_MAX_SIZE ?= 0x20000
434CFG_PAGEABLE_ADDR ?= 0
435CFG_PSCI_ARM32 ?= y
436CFG_SECURE_TIME_SOURCE_REE ?= y
437CFG_UART_BASE ?= UART1_BASE
438endif
439
440ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8M)))
441$(call force,CFG_IMX_UART,y)
442CFG_IMX_SNVS ?= y
443endif
444
445ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
446CFG_CSU ?= y
447endif
448
449ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
450CFG_HWSUPP_MEM_PERM_WXN = n
451CFG_IMX_WDOG ?= y
452endif
453
454ifeq ($(CFG_ARM64_core),y)
455# arm-v8 platforms
456include core/arch/arm/cpu/cortex-armv8-0.mk
457$(call force,CFG_ARM_GICV3,y)
458$(call force,CFG_GIC,y)
459$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
460$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
461
462CFG_CRYPTO_WITH_CE ?= y
463
464supported-ta-targets = ta_arm64
465endif
466
467CFG_TZDRAM_SIZE ?= 0x01e00000
468CFG_SHMEM_SIZE ?= 0x00200000
469CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE) + $(CFG_DDR_SIZE))
470CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
471
472CFG_NSEC_DDR_0_BASE ?= $(CFG_DRAM_BASE)
473CFG_NSEC_DDR_0_SIZE ?= ($(CFG_DDR_SIZE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE))
474
475CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
476CFG_MMAP_REGIONS ?= 24
477
478# SE05X and OCOTP both implement tee_otp_get_die_id()
479ifeq ($(CFG_NXP_SE05X),y)
480$(call force,CFG_IMX_OCOTP,n)
481endif
482CFG_IMX_OCOTP ?= y
483
484# Almost all platforms include CAAM HW Modules, except the
485# ones forced to be disabled
486CFG_NXP_CAAM ?= n
487
488ifeq ($(CFG_NXP_CAAM),y)
489ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
490CFG_IMX_SC ?= y
491endif
492
493# As NXP CAAM Driver is enabled, disable the small local CAAM driver
494# used just to release Job Rings to Non-Secure world
495$(call force,CFG_IMX_CAAM,n)
496else
497
498ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
499CFG_IMX_CAAM ?= y
500endif
501endif
502
503# Cryptographic configuration
504include core/arch/arm/plat-imx/crypto_conf.mk
505