xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision ace4d69d8e4c5d3ba56ffc76efe116973ac4b708) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate
68
69mx8mn-flavorlist = \
70	mx8mnevk
71
72mx8mp-flavorlist = \
73	mx8mpevk \
74	mx8mp_rsb3720_6g
75
76mx8qm-flavorlist = \
77	mx8qmmek \
78
79mx8qx-flavorlist = \
80	mx8qxpmek \
81
82mx8dxl-flavorlist = \
83	mx8dxlevk \
84
85ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
86$(call force,CFG_MX6,y)
87$(call force,CFG_MX6UL,y)
88$(call force,CFG_TEE_CORE_NB_CORE,1)
89$(call force,CFG_TZC380,y)
90include core/arch/arm/cpu/cortex-a7.mk
91else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
92$(call force,CFG_MX6,y)
93$(call force,CFG_MX6ULL,y)
94$(call force,CFG_TEE_CORE_NB_CORE,1)
95$(call force,CFG_TZC380,y)
96$(call force,CFG_IMX_CAAM,n)
97$(call force,CFG_NXP_CAAM,n)
98$(call force,CFG_IMX_DCP,y)
99include core/arch/arm/cpu/cortex-a7.mk
100else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
101$(call force,CFG_MX6,y)
102$(call force,CFG_MX6Q,y)
103$(call force,CFG_TEE_CORE_NB_CORE,4)
104$(call force,CFG_TZC380,y)
105else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
106$(call force,CFG_MX6,y)
107$(call force,CFG_MX6QP,y)
108$(call force,CFG_TEE_CORE_NB_CORE,4)
109else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
110$(call force,CFG_MX6,y)
111$(call force,CFG_MX6D,y)
112$(call force,CFG_TEE_CORE_NB_CORE,2)
113$(call force,CFG_TZC380,y)
114else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
115$(call force,CFG_MX6,y)
116$(call force,CFG_MX6DL,y)
117$(call force,CFG_TEE_CORE_NB_CORE,2)
118$(call force,CFG_TZC380,y)
119else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
120$(call force,CFG_MX6,y)
121$(call force,CFG_MX6S,y)
122$(call force,CFG_TEE_CORE_NB_CORE,1)
123else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
124$(call force,CFG_MX6,y)
125$(call force,CFG_MX6SL,y)
126$(call force,CFG_TEE_CORE_NB_CORE,1)
127$(call force,CFG_IMX_CAAM,n)
128$(call force,CFG_NXP_CAAM,n)
129$(call force,CFG_IMX_DCP,y)
130else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
131$(call force,CFG_MX6,y)
132$(call force,CFG_MX6SLL,y)
133$(call force,CFG_TEE_CORE_NB_CORE,1)
134$(call force,CFG_IMX_CAAM,n)
135$(call force,CFG_NXP_CAAM,n)
136$(call force,CFG_IMX_DCP,y)
137$(call force,CFG_NO_SMP,y)
138else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
139$(call force,CFG_MX6,y)
140$(call force,CFG_MX6SX,y)
141$(call force,CFG_TEE_CORE_NB_CORE,1)
142else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
143$(call force,CFG_MX7,y)
144$(call force,CFG_TEE_CORE_NB_CORE,1)
145include core/arch/arm/cpu/cortex-a7.mk
146else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
147$(call force,CFG_MX7,y)
148$(call force,CFG_TEE_CORE_NB_CORE,2)
149include core/arch/arm/cpu/cortex-a7.mk
150else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
151$(call force,CFG_MX7ULP,y)
152$(call force,CFG_TEE_CORE_NB_CORE,1)
153$(call force,CFG_TZC380,n)
154$(call force,CFG_CSU,n)
155$(call force,CFG_NXP_CAAM,n)
156include core/arch/arm/cpu/cortex-a7.mk
157else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
158$(call force,CFG_MX8MQ,y)
159$(call force,CFG_MX8M,y)
160$(call force,CFG_ARM64_core,y)
161CFG_IMX_UART ?= y
162CFG_DRAM_BASE ?= 0x40000000
163CFG_TEE_CORE_NB_CORE ?= 4
164else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
165$(call force,CFG_MX8MM,y)
166$(call force,CFG_MX8M,y)
167$(call force,CFG_ARM64_core,y)
168CFG_IMX_UART ?= y
169CFG_DRAM_BASE ?= 0x40000000
170CFG_TEE_CORE_NB_CORE ?= 4
171else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
172$(call force,CFG_MX8MN,y)
173$(call force,CFG_MX8M,y)
174$(call force,CFG_ARM64_core,y)
175CFG_IMX_UART ?= y
176CFG_DRAM_BASE ?= 0x40000000
177CFG_TEE_CORE_NB_CORE ?= 4
178else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
179$(call force,CFG_MX8MP,y)
180$(call force,CFG_MX8M,y)
181$(call force,CFG_ARM64_core,y)
182CFG_IMX_UART ?= y
183CFG_DRAM_BASE ?= 0x40000000
184CFG_TEE_CORE_NB_CORE ?= 4
185else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
186$(call force,CFG_MX8QM,y)
187$(call force,CFG_ARM64_core,y)
188$(call force,CFG_IMX_SNVS,n)
189CFG_IMX_LPUART ?= y
190CFG_DRAM_BASE ?= 0x80000000
191CFG_TEE_CORE_NB_CORE ?= 6
192$(call force,CFG_IMX_OCOTP,n)
193else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
194$(call force,CFG_MX8QX,y)
195$(call force,CFG_ARM64_core,y)
196$(call force,CFG_IMX_SNVS,n)
197CFG_IMX_LPUART ?= y
198CFG_DRAM_BASE ?= 0x80000000
199CFG_TEE_CORE_NB_CORE ?= 4
200$(call force,CFG_IMX_OCOTP,n)
201else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
202$(call force,CFG_MX8DXL,y)
203$(call force,CFG_ARM64_core,y)
204$(call force,CFG_IMX_SNVS,n)
205CFG_IMX_LPUART ?= y
206CFG_DRAM_BASE ?= 0x80000000
207$(call force,CFG_TEE_CORE_NB_CORE,2)
208$(call force,CFG_IMX_OCOTP,n)
209$(call force,CFG_NXP_CAAM,n)
210else
211$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
212endif
213
214ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
215CFG_DDR_SIZE ?= 0x40000000
216CFG_NS_ENTRY_ADDR ?= 0x80800000
217CFG_IMX_WDOG_EXT_RESET ?= y
218endif
219
220ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
221CFG_DDR_SIZE ?= 0x40000000
222CFG_UART_BASE ?= UART1_BASE
223CFG_IMX_WDOG_EXT_RESET ?= y
224endif
225
226ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
227CFG_DDR_SIZE ?= 0x20000000
228CFG_NS_ENTRY_ADDR ?= 0x87800000
229CFG_DT_ADDR ?= 0x83100000
230CFG_UART_BASE ?= UART5_BASE
231CFG_BOOT_SECONDARY_REQUEST ?= n
232CFG_EXTERNAL_DTB_OVERLAY ?= y
233CFG_IMX_WDOG_EXT_RESET ?= y
234endif
235
236ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
237CFG_DDR_SIZE ?= 0x20000000
238CFG_NS_ENTRY_ADDR ?= 0x80800000
239CFG_BOOT_SECONDARY_REQUEST ?= n
240endif
241
242ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
243CFG_DDR_SIZE ?= 0x20000000
244CFG_NS_ENTRY_ADDR ?= 0x87800000
245CFG_DT_ADDR ?= 0x83100000
246CFG_BOOT_SECONDARY_REQUEST ?= n
247CFG_EXTERNAL_DTB_OVERLAY = y
248CFG_IMX_WDOG_EXT_RESET = y
249endif
250
251ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
252CFG_DDR_SIZE ?= 0x40000000
253CFG_NS_ENTRY_ADDR ?= 0x60800000
254CFG_UART_BASE ?= UART4_BASE
255endif
256
257ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
258	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
259	mx6dapalis mx6qapalis))
260CFG_DDR_SIZE ?= 0x40000000
261CFG_NS_ENTRY_ADDR ?= 0x12000000
262endif
263
264ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
265	mx6dlsabreauto mx6solosabreauto))
266CFG_DDR_SIZE ?= 0x80000000
267CFG_NS_ENTRY_ADDR ?= 0x12000000
268CFG_UART_BASE ?= UART4_BASE
269endif
270
271ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
272CFG_DDR_SIZE ?= 0x80000000
273CFG_UART_BASE ?= UART1_BASE
274endif
275
276ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
277CFG_DDR_SIZE ?= 0x40000000
278CFG_NS_ENTRY_ADDR ?= 0x12000000
279endif
280
281ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
282CFG_DDR_SIZE ?= 0x40000000
283CFG_NS_ENTRY_ADDR ?= 0x12000000
284CFG_UART_BASE ?= UART2_BASE
285endif
286
287ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
288CFG_NS_ENTRY_ADDR ?= 0x80800000
289CFG_DDR_SIZE ?= 0x40000000
290endif
291
292ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
293CFG_NS_ENTRY_ADDR ?= 0x80800000
294CFG_DDR_SIZE ?= 0x80000000
295endif
296
297ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
298CFG_DDR_SIZE ?= 0x80000000
299CFG_NS_ENTRY_ADDR ?= 0x80800000
300endif
301
302ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
303CFG_DDR_SIZE ?= 0x40000000
304CFG_NS_ENTRY_ADDR ?= 0x80800000
305endif
306
307ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
308CFG_DDR_SIZE ?= 0x40000000
309CFG_UART_BASE ?= UART1_BASE
310endif
311
312ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
313CFG_DDR_SIZE ?= 0x20000000
314CFG_NS_ENTRY_ADDR ?= 0x80800000
315endif
316
317ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
318CFG_DDR_SIZE ?= 0x10000000
319CFG_NS_ENTRY_ADDR ?= 0x80800000
320CFG_UART_BASE ?= UART5_BASE
321endif
322
323ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
324CFG_DDR_SIZE ?= 0x10000000
325CFG_NS_ENTRY_ADDR ?= 0x80800000
326endif
327
328ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
329CFG_DDR_SIZE ?= 0x10000000
330CFG_UART_BASE ?= UART7_BASE
331endif
332
333ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
334CFG_DDR_SIZE ?= 0xc0000000
335CFG_UART_BASE ?= UART1_BASE
336endif
337
338ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
339CFG_DDR_SIZE ?= 0x80000000
340CFG_UART_BASE ?= UART2_BASE
341endif
342
343ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
344CFG_DDR_SIZE ?= 0x40000000
345CFG_UART_BASE ?= UART3_BASE
346CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
347CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
348endif
349
350ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
351CFG_DDR_SIZE ?= 0x80000000
352CFG_UART_BASE ?= UART2_BASE
353endif
354
355ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
356CFG_DDR_SIZE ?= UL(0x180000000)
357CFG_UART_BASE ?= UART2_BASE
358$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
359$(call force,CFG_CORE_ARM64_PA_BITS,36)
360endif
361
362ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
363CFG_DDR_SIZE ?= UL(0x180000000)
364CFG_UART_BASE ?= UART3_BASE
365CFG_TZDRAM_START ?= 0x56000000
366$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
367$(call force,CFG_CORE_ARM64_PA_BITS,36)
368endif
369
370ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
371CFG_DDR_SIZE ?= 0x80000000
372CFG_UART_BASE ?= UART0_BASE
373CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
374CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
375CFG_CORE_ARM64_PA_BITS ?= 40
376endif
377
378ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
379CFG_DDR_SIZE ?= 0x40000000
380CFG_UART_BASE ?= UART0_BASE
381endif
382
383# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
384ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
385	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
386include core/arch/arm/cpu/cortex-a9.mk
387
388$(call force,CFG_PL310,y)
389
390CFG_PL310_LOCKED ?= y
391CFG_ENABLE_SCTLR_RR ?= y
392CFG_SCU ?= y
393endif
394
395ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
396CFG_DRAM_BASE ?= 0x10000000
397endif
398
399ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
400	$(CFG_MX6SX)))
401CFG_DRAM_BASE ?= 0x80000000
402endif
403
404ifeq ($(filter y, $(CFG_MX7)), y)
405CFG_INIT_CNTVOFF ?= y
406CFG_DRAM_BASE ?= 0x80000000
407endif
408
409ifeq ($(filter y, $(CFG_MX7ULP)), y)
410CFG_INIT_CNTVOFF ?= y
411CFG_DRAM_BASE ?= UL(0x60000000)
412$(call force,CFG_IMX_LPUART,y)
413$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
414endif
415
416ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
417$(call force,CFG_GIC,y)
418
419CFG_BOOT_SECONDARY_REQUEST ?= y
420CFG_DT ?= y
421CFG_DTB_MAX_SIZE ?= 0x20000
422CFG_PAGEABLE_ADDR ?= 0
423CFG_PSCI_ARM32 ?= y
424CFG_SECURE_TIME_SOURCE_REE ?= y
425CFG_UART_BASE ?= UART1_BASE
426endif
427
428ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8MM)))
429$(call force,CFG_IMX_UART,y)
430ifeq ($(CFG_RPMB_FS),y)
431CFG_IMX_SNVS ?= y
432endif
433endif
434
435ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
436CFG_CSU ?= y
437endif
438
439ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
440CFG_HWSUPP_MEM_PERM_WXN = n
441CFG_IMX_WDOG ?= y
442endif
443
444ifeq ($(CFG_ARM64_core),y)
445# arm-v8 platforms
446include core/arch/arm/cpu/cortex-armv8-0.mk
447$(call force,CFG_ARM_GICV3,y)
448$(call force,CFG_GIC,y)
449$(call force,CFG_WITH_LPAE,y)
450$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
451$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
452
453CFG_CRYPTO_WITH_CE ?= y
454
455supported-ta-targets = ta_arm64
456endif
457
458CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - 0x02000000 + $(CFG_DDR_SIZE))
459CFG_TZDRAM_SIZE ?= 0x01e00000
460CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
461CFG_SHMEM_SIZE ?= 0x00200000
462
463CFG_NSEC_DDR_0_BASE ?= $(CFG_DRAM_BASE)
464CFG_NSEC_DDR_0_SIZE ?= ($(CFG_DDR_SIZE) - 0x02000000)
465
466CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
467CFG_MMAP_REGIONS ?= 24
468
469# SE05X and OCOTP both implement tee_otp_get_die_id()
470ifeq ($(CFG_NXP_SE05X),y)
471$(call force,CFG_IMX_OCOTP,n)
472endif
473CFG_IMX_OCOTP ?= y
474
475# Almost all platforms include CAAM HW Modules, except the
476# ones forced to be disabled
477CFG_NXP_CAAM ?= n
478
479ifeq ($(CFG_NXP_CAAM),y)
480ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
481CFG_IMX_SC ?= y
482endif
483
484# As NXP CAAM Driver is enabled, disable the small local CAAM driver
485# used just to release Job Rings to Non-Secure world
486$(call force,CFG_IMX_CAAM,n)
487else
488
489ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
490CFG_IMX_CAAM ?= y
491endif
492endif
493
494# Cryptographic configuration
495include core/arch/arm/plat-imx/crypto_conf.mk
496