xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision abca35a69f9bea0496cf05e025c3c36e6d5ea68b) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# The default value CFG_INSECURE ?= y is assigned in mk/config.mk.
4# But mk/config.mk is included after $(platform-dir)/conf.mk from
5# core/core.mk.
6# Since we are making decision based on CFG_INSECURE in this file
7# so we need to set it early here also.
8CFG_INSECURE ?= y
9
10# Get SoC associated with the PLATFORM_FLAVOR
11mx6ul-flavorlist = \
12	mx6ulevk \
13	mx6ul9x9evk \
14	mx6ulccimx6ulsbcpro \
15	mx6ulccbv2 \
16
17mx6ull-flavorlist = \
18	mx6ullevk \
19	mx6ulzevk \
20
21mx6q-flavorlist = \
22	mx6qsabrelite \
23	mx6qsabreauto \
24	mx6qsabresd \
25	mx6qhmbedge \
26	mx6qapalis \
27
28mx6qp-flavorlist = \
29	mx6qpsabreauto \
30	mx6qpsabresd \
31
32mx6sl-flavorlist = \
33	mx6slevk
34
35mx6sll-flavorlist = \
36	mx6sllevk
37
38mx6sx-flavorlist = \
39	mx6sxsabreauto \
40	mx6sxsabresd \
41	mx6sxudooneofull \
42
43mx6d-flavorlist = \
44	mx6dhmbedge \
45	mx6dapalis \
46
47mx6dl-flavorlist = \
48	mx6dlsabreauto \
49	mx6dlsabresd \
50	mx6dlhmbedge \
51
52mx6s-flavorlist = \
53	mx6shmbedge \
54	mx6solosabresd \
55	mx6solosabreauto \
56
57mx7d-flavorlist = \
58	mx7dsabresd \
59	mx7dpico_mbl \
60	mx7dclsom \
61
62mx7s-flavorlist = \
63	mx7swarp7 \
64	mx7swarp7_mbl \
65
66mx7ulp-flavorlist = \
67	mx7ulpevk
68
69mx8mq-flavorlist = \
70	mx8mqevk
71
72mx8mm-flavorlist = \
73	mx8mmevk \
74	mx8mm_cl_iot_gate \
75	mx8mm_phyboard_polis \
76	mx8mm_phygate_tauri_l
77
78mx8mn-flavorlist = \
79	mx8mnevk
80
81mx8mp-flavorlist = \
82	mx8mpevk \
83	mx8mp_rsb3720_6g \
84	mx8mp_phyboard_pollux \
85	mx8mp_libra_fpsc
86
87mx8qm-flavorlist = \
88	mx8qmmek \
89
90mx8qx-flavorlist = \
91	mx8qxpmek \
92	mx8dxmek \
93
94mx8dxl-flavorlist = \
95	mx8dxlevk \
96
97mx8ulp-flavorlist = \
98	mx8ulpevk \
99
100mx93-flavorlist = \
101	mx93evk \
102
103mx95-flavorlist = \
104	mx95evk \
105
106mx91-flavorlist = \
107	mx91evk \
108
109mx943-flavorlist = \
110	mx943evk \
111
112ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
113$(call force,CFG_MX6,y)
114$(call force,CFG_MX6UL,y)
115$(call force,CFG_TEE_CORE_NB_CORE,1)
116$(call force,CFG_TZC380,y)
117include core/arch/arm/cpu/cortex-a7.mk
118else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
119$(call force,CFG_MX6,y)
120$(call force,CFG_MX6ULL,y)
121$(call force,CFG_TEE_CORE_NB_CORE,1)
122$(call force,CFG_TZC380,y)
123$(call force,CFG_IMX_CAAM,n)
124$(call force,CFG_NXP_CAAM,n)
125$(call force,CFG_IMX_DCP,y)
126include core/arch/arm/cpu/cortex-a7.mk
127else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
128$(call force,CFG_MX6,y)
129$(call force,CFG_MX6Q,y)
130$(call force,CFG_TEE_CORE_NB_CORE,4)
131$(call force,CFG_TZC380,y)
132$(call force,CFG_CORE_HAS_GENERIC_TIMER,n)
133else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
134$(call force,CFG_MX6,y)
135$(call force,CFG_MX6QP,y)
136$(call force,CFG_TEE_CORE_NB_CORE,4)
137$(call force,CFG_CORE_HAS_GENERIC_TIMER,n)
138else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
139$(call force,CFG_MX6,y)
140$(call force,CFG_MX6D,y)
141$(call force,CFG_TEE_CORE_NB_CORE,2)
142$(call force,CFG_TZC380,y)
143$(call force,CFG_CORE_HAS_GENERIC_TIMER,n)
144else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
145$(call force,CFG_MX6,y)
146$(call force,CFG_MX6DL,y)
147$(call force,CFG_TEE_CORE_NB_CORE,2)
148$(call force,CFG_TZC380,y)
149$(call force,CFG_CORE_HAS_GENERIC_TIMER,n)
150else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
151$(call force,CFG_MX6,y)
152$(call force,CFG_MX6S,y)
153$(call force,CFG_TEE_CORE_NB_CORE,1)
154$(call force,CFG_CORE_HAS_GENERIC_TIMER,n)
155else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
156$(call force,CFG_MX6,y)
157$(call force,CFG_MX6SL,y)
158$(call force,CFG_TEE_CORE_NB_CORE,1)
159$(call force,CFG_IMX_CAAM,n)
160$(call force,CFG_NXP_CAAM,n)
161$(call force,CFG_IMX_DCP,y)
162$(call force,CFG_CORE_HAS_GENERIC_TIMER,n)
163else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
164$(call force,CFG_MX6,y)
165$(call force,CFG_MX6SLL,y)
166$(call force,CFG_TEE_CORE_NB_CORE,1)
167$(call force,CFG_IMX_CAAM,n)
168$(call force,CFG_NXP_CAAM,n)
169$(call force,CFG_IMX_DCP,y)
170$(call force,CFG_NO_SMP,y)
171$(call force,CFG_CORE_HAS_GENERIC_TIMER,n)
172else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
173$(call force,CFG_MX6,y)
174$(call force,CFG_MX6SX,y)
175$(call force,CFG_TEE_CORE_NB_CORE,1)
176$(call force,CFG_CORE_HAS_GENERIC_TIMER,n)
177else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
178$(call force,CFG_MX7,y)
179$(call force,CFG_TEE_CORE_NB_CORE,1)
180include core/arch/arm/cpu/cortex-a7.mk
181else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
182$(call force,CFG_MX7,y)
183$(call force,CFG_TEE_CORE_NB_CORE,2)
184include core/arch/arm/cpu/cortex-a7.mk
185else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
186$(call force,CFG_MX7ULP,y)
187$(call force,CFG_TEE_CORE_NB_CORE,1)
188$(call force,CFG_TZC380,n)
189$(call force,CFG_IMX_CSU,n)
190include core/arch/arm/cpu/cortex-a7.mk
191else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
192$(call force,CFG_MX8MQ,y)
193$(call force,CFG_MX8M,y)
194$(call force,CFG_ARM64_core,y)
195$(call force,CFG_TZC380,y)
196CFG_DRAM_BASE ?= 0x40000000
197CFG_TEE_CORE_NB_CORE ?= 4
198else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
199$(call force,CFG_MX8MM,y)
200$(call force,CFG_MX8M,y)
201$(call force,CFG_ARM64_core,y)
202$(call force,CFG_TZC380,y)
203CFG_DRAM_BASE ?= 0x40000000
204CFG_TEE_CORE_NB_CORE ?= 4
205else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
206$(call force,CFG_MX8MN,y)
207$(call force,CFG_MX8M,y)
208$(call force,CFG_ARM64_core,y)
209$(call force,CFG_TZC380,y)
210CFG_DRAM_BASE ?= 0x40000000
211CFG_TEE_CORE_NB_CORE ?= 4
212else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
213$(call force,CFG_MX8MP,y)
214$(call force,CFG_MX8M,y)
215$(call force,CFG_ARM64_core,y)
216$(call force,CFG_TZC380,y)
217CFG_DRAM_BASE ?= 0x40000000
218CFG_TEE_CORE_NB_CORE ?= 4
219else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
220$(call force,CFG_MX8QM,y)
221$(call force,CFG_ARM64_core,y)
222$(call force,CFG_IMX_SNVS,n)
223CFG_IMX_LPUART ?= y
224CFG_DRAM_BASE ?= 0x80000000
225CFG_TEE_CORE_NB_CORE ?= 6
226$(call force,CFG_IMX_OCOTP,n)
227else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
228$(call force,CFG_MX8QX,y)
229$(call force,CFG_ARM64_core,y)
230$(call force,CFG_IMX_SNVS,n)
231CFG_IMX_LPUART ?= y
232CFG_DRAM_BASE ?= 0x80000000
233CFG_TEE_CORE_NB_CORE ?= 4
234$(call force,CFG_IMX_OCOTP,n)
235else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8dxl-flavorlist)))
236$(call force,CFG_MX8DXL,y)
237$(call force,CFG_ARM64_core,y)
238$(call force,CFG_IMX_SNVS,n)
239CFG_IMX_LPUART ?= y
240CFG_DRAM_BASE ?= 0x80000000
241$(call force,CFG_TEE_CORE_NB_CORE,2)
242$(call force,CFG_IMX_OCOTP,n)
243else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8ulp-flavorlist)))
244$(call force,CFG_MX8ULP,y)
245$(call force,CFG_ARM64_core,y)
246CFG_IMX_LPUART ?= y
247CFG_DRAM_BASE ?= 0x80000000
248CFG_TEE_CORE_NB_CORE ?= 2
249$(call force,CFG_NXP_SNVS,n)
250$(call force,CFG_IMX_OCOTP,n)
251CFG_IMX_MU ?= y
252CFG_IMX_ELE ?= n
253else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx93-flavorlist)))
254$(call force,CFG_MX93,y)
255$(call force,CFG_ARM64_core,y)
256CFG_IMX_LPUART ?= y
257CFG_DRAM_BASE ?= 0x80000000
258CFG_TEE_CORE_NB_CORE ?= 2
259$(call force,CFG_NXP_SNVS,n)
260$(call force,CFG_IMX_OCOTP,n)
261$(call force,CFG_TZC380,n)
262$(call force,CFG_CRYPTO_DRIVER,n)
263$(call force,CFG_NXP_CAAM,n)
264CFG_IMX_MU ?= y
265CFG_IMX_ELE ?= y
266else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx95-flavorlist)))
267$(call force,CFG_MX95,y)
268$(call force,CFG_ARM64_core,y)
269CFG_IMX_LPUART ?= y
270CFG_DRAM_BASE ?= 0x80000000
271CFG_TEE_CORE_NB_CORE ?= 6
272$(call force,CFG_NXP_SNVS,n)
273$(call force,CFG_IMX_OCOTP,n)
274$(call force,CFG_TZC380,n)
275$(call force,CFG_NXP_CAAM,n)
276CFG_IMX_MU ?= y
277CFG_IMX_ELE ?= y
278else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx91-flavorlist)))
279$(call force,CFG_MX91,y)
280$(call force,CFG_ARM64_core,y)
281CFG_IMX_LPUART ?= y
282CFG_DRAM_BASE ?= 0x80000000
283CFG_TEE_CORE_NB_CORE ?= 1
284$(call force,CFG_NXP_SNVS,n)
285$(call force,CFG_IMX_OCOTP,n)
286$(call force,CFG_TZC380,n)
287$(call force,CFG_NXP_CAAM,n)
288CFG_IMX_MU ?= y
289CFG_IMX_ELE ?= y
290else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx943-flavorlist)))
291$(call force,CFG_MX943,y)
292$(call force,CFG_ARM64_core,y)
293CFG_IMX_LPUART ?= y
294CFG_DRAM_BASE ?= 0x80000000
295CFG_TEE_CORE_NB_CORE ?= 4
296$(call force,CFG_NXP_SNVS,n)
297$(call force,CFG_IMX_OCOTP,n)
298$(call force,CFG_TZC380,n)
299$(call force,CFG_NXP_CAAM,n)
300CFG_IMX_MU ?= y
301CFG_IMX_ELE ?= y
302else
303$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
304endif
305
306ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
307CFG_DDR_SIZE ?= 0x40000000
308CFG_NS_ENTRY_ADDR ?= 0x80800000
309CFG_IMX_WDOG_EXT_RESET ?= y
310endif
311
312ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
313CFG_DDR_SIZE ?= 0x40000000
314CFG_UART_BASE ?= UART1_BASE
315CFG_IMX_WDOG_EXT_RESET ?= y
316endif
317
318ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
319CFG_DDR_SIZE ?= 0x20000000
320CFG_NS_ENTRY_ADDR ?= 0x87800000
321CFG_DT_ADDR ?= 0x83100000
322CFG_UART_BASE ?= UART5_BASE
323CFG_BOOT_SECONDARY_REQUEST ?= n
324CFG_EXTERNAL_DTB_OVERLAY ?= y
325CFG_IMX_WDOG_EXT_RESET ?= y
326endif
327
328ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
329CFG_DDR_SIZE ?= 0x20000000
330CFG_NS_ENTRY_ADDR ?= 0x80800000
331CFG_BOOT_SECONDARY_REQUEST ?= n
332endif
333
334ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
335CFG_DDR_SIZE ?= 0x20000000
336CFG_NS_ENTRY_ADDR ?= 0x87800000
337CFG_DT_ADDR ?= 0x83100000
338CFG_BOOT_SECONDARY_REQUEST ?= n
339CFG_EXTERNAL_DTB_OVERLAY = y
340CFG_IMX_WDOG_EXT_RESET = y
341endif
342
343ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
344CFG_DDR_SIZE ?= 0x40000000
345CFG_NS_ENTRY_ADDR ?= 0x60800000
346CFG_UART_BASE ?= UART4_BASE
347endif
348
349ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
350	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
351	mx6dapalis mx6qapalis))
352CFG_DDR_SIZE ?= 0x40000000
353CFG_NS_ENTRY_ADDR ?= 0x12000000
354endif
355
356ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
357	mx6dlsabreauto mx6solosabreauto))
358CFG_DDR_SIZE ?= 0x80000000
359CFG_NS_ENTRY_ADDR ?= 0x12000000
360CFG_UART_BASE ?= UART4_BASE
361endif
362
363ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
364CFG_DDR_SIZE ?= 0x80000000
365CFG_UART_BASE ?= UART1_BASE
366endif
367
368ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
369CFG_DDR_SIZE ?= 0x40000000
370CFG_NS_ENTRY_ADDR ?= 0x12000000
371endif
372
373ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
374CFG_DDR_SIZE ?= 0x40000000
375CFG_NS_ENTRY_ADDR ?= 0x12000000
376CFG_UART_BASE ?= UART2_BASE
377endif
378
379ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
380CFG_NS_ENTRY_ADDR ?= 0x80800000
381CFG_DDR_SIZE ?= 0x40000000
382endif
383
384ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
385CFG_NS_ENTRY_ADDR ?= 0x80800000
386CFG_DDR_SIZE ?= 0x80000000
387endif
388
389ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
390CFG_DDR_SIZE ?= 0x80000000
391CFG_NS_ENTRY_ADDR ?= 0x80800000
392endif
393
394ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
395CFG_DDR_SIZE ?= 0x40000000
396CFG_NS_ENTRY_ADDR ?= 0x80800000
397endif
398
399ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
400CFG_DDR_SIZE ?= 0x40000000
401CFG_UART_BASE ?= UART1_BASE
402endif
403
404ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
405CFG_DDR_SIZE ?= 0x20000000
406CFG_NS_ENTRY_ADDR ?= 0x80800000
407endif
408
409ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
410CFG_DDR_SIZE ?= 0x10000000
411CFG_NS_ENTRY_ADDR ?= 0x80800000
412CFG_UART_BASE ?= UART5_BASE
413endif
414
415ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
416CFG_DDR_SIZE ?= 0x10000000
417CFG_NS_ENTRY_ADDR ?= 0x80800000
418endif
419
420ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
421CFG_DDR_SIZE ?= 0x10000000
422CFG_UART_BASE ?= UART7_BASE
423endif
424
425ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
426CFG_DDR_SIZE ?= 0xc0000000
427CFG_UART_BASE ?= UART1_BASE
428endif
429
430ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
431CFG_DDR_SIZE ?= 0x80000000
432CFG_UART_BASE ?= UART2_BASE
433endif
434
435ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
436CFG_DDR_SIZE ?= 0x40000000
437CFG_UART_BASE ?= UART3_BASE
438CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
439CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
440endif
441
442ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phyboard_polis))
443CFG_DDR_SIZE ?= 0x40000000
444CFG_UART_BASE ?= UART3_BASE
445$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
446$(call force,CFG_CORE_ARM64_PA_BITS,36)
447endif
448
449ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_phygate_tauri_l))
450CFG_DDR_SIZE ?= 0x80000000
451CFG_UART_BASE ?= UART3_BASE
452$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
453$(call force,CFG_CORE_ARM64_PA_BITS,36)
454endif
455
456ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
457CFG_DDR_SIZE ?= 0x80000000
458CFG_UART_BASE ?= UART2_BASE
459endif
460
461ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
462CFG_DDR_SIZE ?= UL(0x180000000)
463CFG_UART_BASE ?= UART2_BASE
464$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
465$(call force,CFG_CORE_ARM64_PA_BITS,36)
466$(call force,CFG_LPAE_ADDR_SPACE_BITS,36)
467endif
468
469ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_libra_fpsc))
470CFG_DDR_SIZE ?= 0x40000000
471CFG_UART_BASE ?= UART4_BASE
472$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
473$(call force,CFG_CORE_ARM64_PA_BITS,36)
474endif
475
476ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_phyboard_pollux))
477CFG_DDR_SIZE ?= 0x40000000
478CFG_UART_BASE ?= UART1_BASE
479$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
480$(call force,CFG_CORE_ARM64_PA_BITS,36)
481endif
482
483ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
484CFG_DDR_SIZE ?= UL(0x180000000)
485CFG_UART_BASE ?= UART3_BASE
486CFG_TZDRAM_START ?= 0x56000000
487$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
488$(call force,CFG_CORE_ARM64_PA_BITS,36)
489endif
490
491ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
492CFG_DDR_SIZE ?= 0x80000000
493CFG_UART_BASE ?= UART0_BASE
494CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
495CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
496CFG_CORE_ARM64_PA_BITS ?= 40
497endif
498
499ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxmek))
500CFG_DDR_SIZE ?= 0x40000000
501CFG_UART_BASE ?= UART0_BASE
502$(call force,CFG_MX8DX,y)
503endif
504
505ifneq (,$(filter $(PLATFORM_FLAVOR),mx8dxlevk))
506CFG_DDR_SIZE ?= 0x40000000
507CFG_UART_BASE ?= UART0_BASE
508CFG_NSEC_DDR_1_BASE ?= 0x800000000UL
509CFG_NSEC_DDR_1_SIZE ?= 0x400000000UL
510CFG_CORE_ARM64_PA_BITS ?= 40
511endif
512
513ifneq (,$(filter $(PLATFORM_FLAVOR),mx8ulpevk))
514CFG_DDR_SIZE ?= 0x80000000
515CFG_UART_BASE ?= UART5_BASE
516endif
517
518ifneq (,$(filter $(PLATFORM_FLAVOR),mx93evk mx91evk))
519CFG_DDR_SIZE ?= 0x80000000
520CFG_UART_BASE ?= UART1_BASE
521endif
522
523ifneq (,$(filter $(PLATFORM_FLAVOR),mx95evk mx943evk))
524CFG_DDR_SIZE ?= 0x80000000
525CFG_UART_BASE ?= UART1_BASE
526CFG_NSEC_DDR_1_BASE ?= 0x100000000UL
527CFG_NSEC_DDR_1_SIZE ?= 0x380000000UL
528CFG_CORE_ARM64_PA_BITS ?= 40
529endif
530
531# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
532ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
533	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
534include core/arch/arm/cpu/cortex-a9.mk
535
536$(call force,CFG_PL310,y)
537
538CFG_PL310_LOCKED ?= y
539CFG_ENABLE_SCTLR_RR ?= y
540CFG_IMX_SCU ?= y
541endif
542
543ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
544CFG_DRAM_BASE ?= 0x10000000
545endif
546
547ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
548	$(CFG_MX6SX)))
549CFG_DRAM_BASE ?= 0x80000000
550endif
551
552ifeq ($(filter y, $(CFG_MX7)), y)
553CFG_INIT_CNTVOFF ?= y
554CFG_DRAM_BASE ?= 0x80000000
555endif
556
557ifeq ($(filter y, $(CFG_MX7ULP)), y)
558CFG_INIT_CNTVOFF ?= y
559CFG_DRAM_BASE ?= UL(0x60000000)
560$(call force,CFG_IMX_LPUART,y)
561$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
562endif
563
564ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
565$(call force,CFG_GIC,y)
566
567CFG_BOOT_SECONDARY_REQUEST ?= y
568CFG_DT ?= y
569CFG_DTB_MAX_SIZE ?= 0x20000
570CFG_PAGEABLE_ADDR ?= 0
571CFG_PSCI_ARM32 ?= y
572CFG_SECURE_TIME_SOURCE_REE ?= y
573CFG_UART_BASE ?= UART1_BASE
574endif
575
576ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8M)))
577$(call force,CFG_IMX_UART,y)
578CFG_IMX_SNVS ?= y
579endif
580
581ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
582CFG_IMX_CSU ?= y
583endif
584
585ifneq (,$(filter y, $(CFG_MX8M)))
586ifneq ($(CFG_INSECURE),y)
587$(call force,CFG_TZASC_REGION0_SECURE,y)
588endif
589endif
590
591# We can't make it default because of missing i.MX7 and i.MX9 support.
592# Once all platforms are supported we can remove the CFG_TZASC_CHECK_ENABLED
593# and perform the check always.
594ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX8M)))
595ifneq ($(CFG_INSECURE),y)
596$(call force,CFG_TZASC_CHECK_ENABLED,y)
597endif
598endif
599
600ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
601CFG_HWSUPP_MEM_PERM_WXN = n
602CFG_IMX_WDOG ?= y
603endif
604
605ifeq ($(CFG_ARM64_core),y)
606# arm-v8 platforms
607include core/arch/arm/cpu/cortex-armv8-0.mk
608$(call force,CFG_ARM_GICV3,y)
609$(call force,CFG_GIC,y)
610$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
611$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
612
613CFG_CRYPTO_WITH_CE ?= y
614
615supported-ta-targets = ta_arm64
616endif
617
618CFG_TZDRAM_SIZE ?= 0x01e00000
619CFG_SHMEM_SIZE ?= 0x00200000
620CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - $(CFG_TZDRAM_SIZE) - $(CFG_SHMEM_SIZE) + $(CFG_DDR_SIZE))
621CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
622
623# Enable embedded tests by default
624CFG_ENABLE_EMBEDDED_TESTS ?= y
625CFG_ATTESTATION_PTA ?= y
626
627# Set default heap size for imx platforms to 128k
628CFG_CORE_HEAP_SIZE ?= 131072
629
630CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
631CFG_MMAP_REGIONS ?= 24
632
633# SE05X and OCOTP both implement tee_otp_get_die_id()
634ifeq ($(CFG_NXP_SE05X),y)
635$(call force,CFG_IMX_OCOTP,n)
636$(call force,CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID,n)
637endif
638CFG_IMX_OCOTP ?= y
639CFG_IMX_DIGPROG ?= y
640CFG_PKCS11_TA ?= y
641CFG_CORE_HUK_SUBKEY_COMPAT_USE_OTP_DIE_ID ?= y
642
643# Almost all platforms include CAAM HW Modules, except the
644# ones forced to be disabled
645CFG_NXP_CAAM ?= n
646
647ifeq ($(CFG_NXP_CAAM),y)
648ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX) $(CFG_MX8DXL)), y)
649CFG_IMX_SC ?= y
650CFG_IMX_MU ?= y
651endif
652
653else
654
655ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
656CFG_IMX_CAAM ?= y
657endif
658
659endif
660