xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision 45f25897f4bcac14dc13e2adee7f1f96f117fcde) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8	mx6ulccbv2 \
9
10mx6ull-flavorlist = \
11	mx6ullevk \
12	mx6ulzevk \
13
14mx6q-flavorlist = \
15	mx6qsabrelite \
16	mx6qsabreauto \
17	mx6qsabresd \
18	mx6qhmbedge \
19	mx6qapalis \
20
21mx6qp-flavorlist = \
22	mx6qpsabreauto \
23	mx6qpsabresd \
24
25mx6sl-flavorlist = \
26	mx6slevk
27
28mx6sll-flavorlist = \
29	mx6sllevk
30
31mx6sx-flavorlist = \
32	mx6sxsabreauto \
33	mx6sxsabresd \
34	mx6sxudooneofull \
35
36mx6d-flavorlist = \
37	mx6dhmbedge \
38	mx6dapalis \
39
40mx6dl-flavorlist = \
41	mx6dlsabreauto \
42	mx6dlsabresd \
43	mx6dlhmbedge \
44
45mx6s-flavorlist = \
46	mx6shmbedge \
47	mx6solosabresd \
48	mx6solosabreauto \
49
50mx7d-flavorlist = \
51	mx7dsabresd \
52	mx7dpico_mbl \
53	mx7dclsom \
54
55mx7s-flavorlist = \
56	mx7swarp7 \
57	mx7swarp7_mbl \
58
59mx7ulp-flavorlist = \
60	mx7ulpevk
61
62mx8mq-flavorlist = \
63	mx8mqevk
64
65mx8mm-flavorlist = \
66	mx8mmevk \
67	mx8mm_cl_iot_gate
68
69mx8mn-flavorlist = \
70	mx8mnevk
71
72mx8mp-flavorlist = \
73	mx8mpevk \
74	mx8mp_rsb3720_6g
75
76mx8qm-flavorlist = \
77	mx8qmmek \
78
79mx8qx-flavorlist = \
80	mx8qxpmek \
81
82ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
83$(call force,CFG_MX6,y)
84$(call force,CFG_MX6UL,y)
85$(call force,CFG_TEE_CORE_NB_CORE,1)
86$(call force,CFG_TZC380,y)
87include core/arch/arm/cpu/cortex-a7.mk
88else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
89$(call force,CFG_MX6,y)
90$(call force,CFG_MX6ULL,y)
91$(call force,CFG_TEE_CORE_NB_CORE,1)
92$(call force,CFG_TZC380,y)
93$(call force,CFG_IMX_CAAM,n)
94$(call force,CFG_NXP_CAAM,n)
95$(call force,CFG_IMX_DCP,y)
96include core/arch/arm/cpu/cortex-a7.mk
97else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
98$(call force,CFG_MX6,y)
99$(call force,CFG_MX6Q,y)
100$(call force,CFG_TEE_CORE_NB_CORE,4)
101$(call force,CFG_TZC380,y)
102else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
103$(call force,CFG_MX6,y)
104$(call force,CFG_MX6QP,y)
105$(call force,CFG_TEE_CORE_NB_CORE,4)
106else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
107$(call force,CFG_MX6,y)
108$(call force,CFG_MX6D,y)
109$(call force,CFG_TEE_CORE_NB_CORE,2)
110$(call force,CFG_TZC380,y)
111else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
112$(call force,CFG_MX6,y)
113$(call force,CFG_MX6DL,y)
114$(call force,CFG_TEE_CORE_NB_CORE,2)
115$(call force,CFG_TZC380,y)
116else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
117$(call force,CFG_MX6,y)
118$(call force,CFG_MX6S,y)
119$(call force,CFG_TEE_CORE_NB_CORE,1)
120else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
121$(call force,CFG_MX6,y)
122$(call force,CFG_MX6SL,y)
123$(call force,CFG_TEE_CORE_NB_CORE,1)
124$(call force,CFG_IMX_CAAM,n)
125$(call force,CFG_NXP_CAAM,n)
126$(call force,CFG_IMX_DCP,y)
127else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
128$(call force,CFG_MX6,y)
129$(call force,CFG_MX6SLL,y)
130$(call force,CFG_TEE_CORE_NB_CORE,1)
131$(call force,CFG_IMX_CAAM,n)
132$(call force,CFG_NXP_CAAM,n)
133$(call force,CFG_IMX_DCP,y)
134$(call force,CFG_NO_SMP,y)
135else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
136$(call force,CFG_MX6,y)
137$(call force,CFG_MX6SX,y)
138$(call force,CFG_TEE_CORE_NB_CORE,1)
139else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
140$(call force,CFG_MX7,y)
141$(call force,CFG_TEE_CORE_NB_CORE,1)
142include core/arch/arm/cpu/cortex-a7.mk
143else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
144$(call force,CFG_MX7,y)
145$(call force,CFG_TEE_CORE_NB_CORE,2)
146include core/arch/arm/cpu/cortex-a7.mk
147else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
148$(call force,CFG_MX7ULP,y)
149$(call force,CFG_TEE_CORE_NB_CORE,1)
150$(call force,CFG_TZC380,n)
151$(call force,CFG_CSU,n)
152$(call force,CFG_NXP_CAAM,n)
153include core/arch/arm/cpu/cortex-a7.mk
154else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
155$(call force,CFG_MX8MQ,y)
156$(call force,CFG_MX8M,y)
157$(call force,CFG_ARM64_core,y)
158CFG_IMX_UART ?= y
159CFG_DRAM_BASE ?= 0x40000000
160CFG_TEE_CORE_NB_CORE ?= 4
161else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
162$(call force,CFG_MX8MM,y)
163$(call force,CFG_MX8M,y)
164$(call force,CFG_ARM64_core,y)
165CFG_IMX_UART ?= y
166CFG_DRAM_BASE ?= 0x40000000
167CFG_TEE_CORE_NB_CORE ?= 4
168else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
169$(call force,CFG_MX8MN,y)
170$(call force,CFG_MX8M,y)
171$(call force,CFG_ARM64_core,y)
172CFG_IMX_UART ?= y
173CFG_DRAM_BASE ?= 0x40000000
174CFG_TEE_CORE_NB_CORE ?= 4
175else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mp-flavorlist)))
176$(call force,CFG_MX8MP,y)
177$(call force,CFG_MX8M,y)
178$(call force,CFG_ARM64_core,y)
179CFG_IMX_UART ?= y
180CFG_DRAM_BASE ?= 0x40000000
181CFG_TEE_CORE_NB_CORE ?= 4
182else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
183$(call force,CFG_MX8QM,y)
184$(call force,CFG_ARM64_core,y)
185$(call force,CFG_IMX_SNVS,n)
186CFG_IMX_LPUART ?= y
187CFG_DRAM_BASE ?= 0x80000000
188CFG_TEE_CORE_NB_CORE ?= 6
189$(call force,CFG_NXP_CAAM,n)
190$(call force,CFG_IMX_OCOTP,n)
191else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
192$(call force,CFG_MX8QX,y)
193$(call force,CFG_ARM64_core,y)
194$(call force,CFG_IMX_SNVS,n)
195CFG_IMX_LPUART ?= y
196CFG_DRAM_BASE ?= 0x80000000
197CFG_TEE_CORE_NB_CORE ?= 4
198$(call force,CFG_NXP_CAAM,n)
199$(call force,CFG_IMX_OCOTP,n)
200else
201$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
202endif
203
204ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
205CFG_DDR_SIZE ?= 0x40000000
206CFG_NS_ENTRY_ADDR ?= 0x80800000
207endif
208
209ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
210CFG_DDR_SIZE ?= 0x40000000
211CFG_UART_BASE ?= UART1_BASE
212endif
213
214ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
215CFG_DDR_SIZE ?= 0x20000000
216CFG_NS_ENTRY_ADDR ?= 0x87800000
217CFG_DT_ADDR ?= 0x83100000
218CFG_UART_BASE ?= UART5_BASE
219CFG_BOOT_SECONDARY_REQUEST ?= n
220CFG_EXTERNAL_DTB_OVERLAY ?= y
221CFG_IMX_WDOG_EXT_RESET ?= y
222endif
223
224ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
225CFG_DDR_SIZE ?= 0x20000000
226CFG_NS_ENTRY_ADDR ?= 0x80800000
227CFG_BOOT_SECONDARY_REQUEST ?= n
228endif
229
230ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
231CFG_DDR_SIZE ?= 0x20000000
232CFG_NS_ENTRY_ADDR ?= 0x87800000
233CFG_DT_ADDR ?= 0x83100000
234CFG_BOOT_SECONDARY_REQUEST ?= n
235CFG_EXTERNAL_DTB_OVERLAY = y
236CFG_IMX_WDOG_EXT_RESET = y
237endif
238
239ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
240CFG_DDR_SIZE ?= 0x40000000
241CFG_NS_ENTRY_ADDR ?= 0x60800000
242CFG_UART_BASE ?= UART4_BASE
243endif
244
245ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
246	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
247	mx6dapalis mx6qapalis))
248CFG_DDR_SIZE ?= 0x40000000
249CFG_NS_ENTRY_ADDR ?= 0x12000000
250endif
251
252ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
253	mx6dlsabreauto mx6solosabreauto))
254CFG_DDR_SIZE ?= 0x80000000
255CFG_NS_ENTRY_ADDR ?= 0x12000000
256CFG_UART_BASE ?= UART4_BASE
257endif
258
259ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
260CFG_DDR_SIZE ?= 0x80000000
261CFG_UART_BASE ?= UART1_BASE
262endif
263
264ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
265CFG_DDR_SIZE ?= 0x40000000
266CFG_NS_ENTRY_ADDR ?= 0x12000000
267endif
268
269ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
270CFG_DDR_SIZE ?= 0x40000000
271CFG_NS_ENTRY_ADDR ?= 0x12000000
272CFG_UART_BASE ?= UART2_BASE
273endif
274
275ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
276CFG_NS_ENTRY_ADDR ?= 0x80800000
277CFG_DDR_SIZE ?= 0x40000000
278endif
279
280ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
281CFG_NS_ENTRY_ADDR ?= 0x80800000
282CFG_DDR_SIZE ?= 0x80000000
283endif
284
285ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
286CFG_DDR_SIZE ?= 0x80000000
287CFG_NS_ENTRY_ADDR ?= 0x80800000
288endif
289
290ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
291CFG_DDR_SIZE ?= 0x40000000
292CFG_NS_ENTRY_ADDR ?= 0x80800000
293endif
294
295ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
296CFG_DDR_SIZE ?= 0x40000000
297CFG_UART_BASE ?= UART1_BASE
298endif
299
300ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
301CFG_DDR_SIZE ?= 0x20000000
302CFG_NS_ENTRY_ADDR ?= 0x80800000
303endif
304
305ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
306CFG_DDR_SIZE ?= 0x10000000
307CFG_NS_ENTRY_ADDR ?= 0x80800000
308CFG_UART_BASE ?= UART5_BASE
309endif
310
311ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
312CFG_DDR_SIZE ?= 0x10000000
313CFG_NS_ENTRY_ADDR ?= 0x80800000
314endif
315
316ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccbv2))
317CFG_DDR_SIZE ?= 0x10000000
318CFG_UART_BASE ?= UART7_BASE
319endif
320
321ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
322CFG_DDR_SIZE ?= 0xc0000000
323CFG_UART_BASE ?= UART1_BASE
324endif
325
326ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
327CFG_DDR_SIZE ?= 0x80000000
328CFG_UART_BASE ?= UART2_BASE
329endif
330
331ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mm_cl_iot_gate))
332CFG_DDR_SIZE ?= 0x40000000
333CFG_UART_BASE ?= UART3_BASE
334CFG_NSEC_DDR_1_BASE ?= 0x80000000UL
335CFG_NSEC_DDR_1_SIZE ?= 0x40000000UL
336endif
337
338ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
339CFG_DDR_SIZE ?= 0x80000000
340CFG_UART_BASE ?= UART2_BASE
341endif
342
343ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mpevk))
344CFG_DDR_SIZE ?= UL(0x180000000)
345CFG_UART_BASE ?= UART2_BASE
346$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
347$(call force,CFG_CORE_ARM64_PA_BITS,36)
348endif
349
350ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mp_rsb3720_6g))
351CFG_DDR_SIZE ?= UL(0x180000000)
352CFG_UART_BASE ?= UART3_BASE
353CFG_TZDRAM_START ?= 0x56000000
354$(call force,CFG_CORE_LARGE_PHYS_ADDR,y)
355$(call force,CFG_CORE_ARM64_PA_BITS,36)
356endif
357
358ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
359CFG_DDR_SIZE ?= 0x80000000
360CFG_UART_BASE ?= UART0_BASE
361CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
362CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
363CFG_CORE_ARM64_PA_BITS ?= 40
364endif
365
366# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
367ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
368	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
369include core/arch/arm/cpu/cortex-a9.mk
370
371$(call force,CFG_PL310,y)
372
373CFG_PL310_LOCKED ?= y
374CFG_ENABLE_SCTLR_RR ?= y
375CFG_SCU ?= y
376endif
377
378ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
379CFG_DRAM_BASE ?= 0x10000000
380endif
381
382ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
383	$(CFG_MX6SX)))
384CFG_DRAM_BASE ?= 0x80000000
385endif
386
387ifeq ($(filter y, $(CFG_MX7)), y)
388CFG_INIT_CNTVOFF ?= y
389CFG_DRAM_BASE ?= 0x80000000
390endif
391
392ifeq ($(filter y, $(CFG_MX7ULP)), y)
393CFG_INIT_CNTVOFF ?= y
394CFG_DRAM_BASE ?= UL(0x60000000)
395$(call force,CFG_IMX_LPUART,y)
396$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
397endif
398
399ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
400$(call force,CFG_GIC,y)
401
402CFG_BOOT_SECONDARY_REQUEST ?= y
403CFG_DT ?= y
404CFG_DTB_MAX_SIZE ?= 0x20000
405CFG_PAGEABLE_ADDR ?= 0
406CFG_PSCI_ARM32 ?= y
407CFG_SECURE_TIME_SOURCE_REE ?= y
408CFG_UART_BASE ?= UART1_BASE
409endif
410
411ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX8MM)))
412$(call force,CFG_IMX_UART,y)
413ifeq ($(CFG_RPMB_FS),y)
414CFG_IMX_SNVS ?= y
415endif
416endif
417
418ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
419CFG_CSU ?= y
420endif
421
422ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
423CFG_HWSUPP_MEM_PERM_WXN = n
424CFG_IMX_WDOG ?= y
425endif
426
427ifeq ($(CFG_ARM64_core),y)
428# arm-v8 platforms
429include core/arch/arm/cpu/cortex-armv8-0.mk
430$(call force,CFG_ARM_GICV3,y)
431$(call force,CFG_GIC,y)
432$(call force,CFG_WITH_LPAE,y)
433$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
434$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
435
436CFG_CRYPTO_WITH_CE ?= y
437
438supported-ta-targets = ta_arm64
439endif
440
441CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - 0x02000000 + $(CFG_DDR_SIZE))
442CFG_TZDRAM_SIZE ?= 0x01e00000
443CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
444CFG_SHMEM_SIZE ?= 0x00200000
445
446CFG_NSEC_DDR_0_BASE ?= $(CFG_DRAM_BASE)
447CFG_NSEC_DDR_0_SIZE ?= ($(CFG_DDR_SIZE) - 0x02000000)
448
449CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
450CFG_MMAP_REGIONS ?= 24
451
452# SE05X and OCOTP both implement tee_otp_get_die_id()
453ifeq ($(CFG_NXP_SE05X),y)
454$(call force,CFG_IMX_OCOTP,n)
455endif
456CFG_IMX_OCOTP ?= y
457
458# Almost all platforms include CAAM HW Modules, except the
459# ones forced to be disabled
460CFG_NXP_CAAM ?= n
461
462ifeq ($(CFG_NXP_CAAM),y)
463ifeq ($(filter y, $(CFG_MX8QM) $(CFG_MX8QX)), y)
464CFG_IMX_SC ?= y
465endif
466
467# As NXP CAAM Driver is enabled, disable the small local CAAM driver
468# used just to release Job Rings to Non-Secure world
469$(call force,CFG_IMX_CAAM,n)
470else
471
472ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
473CFG_IMX_CAAM ?= y
474endif
475endif
476
477# Cryptographic configuration
478include core/arch/arm/plat-imx/crypto_conf.mk
479