xref: /optee_os/core/arch/arm/plat-imx/conf.mk (revision 2c028fdebbedee91f88f6c5325b5064a124dfe46) 
1PLATFORM_FLAVOR ?= mx6ulevk
2
3# Get SoC associated with the PLATFORM_FLAVOR
4mx6ul-flavorlist = \
5	mx6ulevk \
6	mx6ul9x9evk \
7	mx6ulccimx6ulsbcpro \
8
9mx6ull-flavorlist = \
10	mx6ullevk \
11	mx6ulzevk \
12
13mx6q-flavorlist = \
14	mx6qsabrelite \
15	mx6qsabreauto \
16	mx6qsabresd \
17	mx6qhmbedge \
18	mx6qapalis \
19
20mx6qp-flavorlist = \
21	mx6qpsabreauto \
22	mx6qpsabresd \
23
24mx6sl-flavorlist = \
25	mx6slevk
26
27mx6sll-flavorlist = \
28	mx6sllevk
29
30mx6sx-flavorlist = \
31	mx6sxsabreauto \
32	mx6sxsabresd \
33	mx6sxudooneofull \
34
35mx6d-flavorlist = \
36	mx6dhmbedge \
37	mx6dapalis \
38
39mx6dl-flavorlist = \
40	mx6dlsabreauto \
41	mx6dlsabresd \
42	mx6dlhmbedge \
43
44mx6s-flavorlist = \
45	mx6shmbedge \
46	mx6solosabresd \
47	mx6solosabreauto \
48
49mx7d-flavorlist = \
50	mx7dsabresd \
51	mx7dpico_mbl \
52	mx7dclsom \
53
54mx7s-flavorlist = \
55	mx7swarp7 \
56	mx7swarp7_mbl \
57
58mx7ulp-flavorlist = \
59	mx7ulpevk
60
61mx8mq-flavorlist = \
62	mx8mqevk
63
64mx8mm-flavorlist = \
65	mx8mmevk
66
67mx8mn-flavorlist = \
68	mx8mnevk
69
70mx8qm-flavorlist = \
71	mx8qmmek \
72
73mx8qx-flavorlist = \
74	mx8qxpmek \
75
76ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ul-flavorlist)))
77$(call force,CFG_MX6,y)
78$(call force,CFG_MX6UL,y)
79$(call force,CFG_TEE_CORE_NB_CORE,1)
80$(call force,CFG_TZC380,y)
81include core/arch/arm/cpu/cortex-a7.mk
82else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6ull-flavorlist)))
83$(call force,CFG_MX6,y)
84$(call force,CFG_MX6ULL,y)
85$(call force,CFG_TEE_CORE_NB_CORE,1)
86$(call force,CFG_IMX_CAAM,n)
87$(call force,CFG_NXP_CAAM,n)
88include core/arch/arm/cpu/cortex-a7.mk
89else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6q-flavorlist)))
90$(call force,CFG_MX6,y)
91$(call force,CFG_MX6Q,y)
92$(call force,CFG_TEE_CORE_NB_CORE,4)
93$(call force,CFG_TZC380,y)
94else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6qp-flavorlist)))
95$(call force,CFG_MX6,y)
96$(call force,CFG_MX6QP,y)
97$(call force,CFG_TEE_CORE_NB_CORE,4)
98else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6d-flavorlist)))
99$(call force,CFG_MX6,y)
100$(call force,CFG_MX6D,y)
101$(call force,CFG_TEE_CORE_NB_CORE,2)
102$(call force,CFG_TZC380,y)
103else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6dl-flavorlist)))
104$(call force,CFG_MX6,y)
105$(call force,CFG_MX6DL,y)
106$(call force,CFG_TEE_CORE_NB_CORE,2)
107$(call force,CFG_TZC380,y)
108else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6s-flavorlist)))
109$(call force,CFG_MX6,y)
110$(call force,CFG_MX6S,y)
111$(call force,CFG_TEE_CORE_NB_CORE,1)
112else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sl-flavorlist)))
113$(call force,CFG_MX6,y)
114$(call force,CFG_MX6SL,y)
115$(call force,CFG_TEE_CORE_NB_CORE,1)
116$(call force,CFG_IMX_CAAM,n)
117$(call force,CFG_NXP_CAAM,n)
118else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sll-flavorlist)))
119$(call force,CFG_MX6,y)
120$(call force,CFG_MX6SLL,y)
121$(call force,CFG_TEE_CORE_NB_CORE,1)
122$(call force,CFG_IMX_CAAM,n)
123$(call force,CFG_NXP_CAAM,n)
124else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx6sx-flavorlist)))
125$(call force,CFG_MX6,y)
126$(call force,CFG_MX6SX,y)
127$(call force,CFG_TEE_CORE_NB_CORE,1)
128else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7s-flavorlist)))
129$(call force,CFG_MX7,y)
130$(call force,CFG_TEE_CORE_NB_CORE,1)
131include core/arch/arm/cpu/cortex-a7.mk
132else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7d-flavorlist)))
133$(call force,CFG_MX7,y)
134$(call force,CFG_TEE_CORE_NB_CORE,2)
135include core/arch/arm/cpu/cortex-a7.mk
136else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx7ulp-flavorlist)))
137$(call force,CFG_MX7ULP,y)
138$(call force,CFG_TEE_CORE_NB_CORE,1)
139$(call force,CFG_TZC380,n)
140$(call force,CFG_CSU,n)
141$(call force,CFG_NXP_CAAM,n)
142include core/arch/arm/cpu/cortex-a7.mk
143else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mq-flavorlist)))
144$(call force,CFG_MX8MQ,y)
145$(call force,CFG_ARM64_core,y)
146CFG_IMX_UART ?= y
147CFG_DRAM_BASE ?= 0x40000000
148CFG_TEE_CORE_NB_CORE ?= 4
149else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mm-flavorlist)))
150$(call force,CFG_MX8MM,y)
151$(call force,CFG_ARM64_core,y)
152CFG_IMX_UART ?= y
153CFG_DRAM_BASE ?= 0x40000000
154CFG_TEE_CORE_NB_CORE ?= 4
155else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8mn-flavorlist)))
156$(call force,CFG_MX8MN,y)
157$(call force,CFG_ARM64_core,y)
158CFG_IMX_UART ?= y
159CFG_DRAM_BASE ?= 0x40000000
160CFG_TEE_CORE_NB_CORE ?= 4
161else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qm-flavorlist)))
162$(call force,CFG_MX8QM,y)
163$(call force,CFG_ARM64_core,y)
164$(call force,CFG_IMX_SNVS,n)
165CFG_IMX_LPUART ?= y
166CFG_DRAM_BASE ?= 0x80000000
167CFG_TEE_CORE_NB_CORE ?= 6
168$(call force,CFG_NXP_CAAM,n)
169else ifneq (,$(filter $(PLATFORM_FLAVOR),$(mx8qx-flavorlist)))
170$(call force,CFG_MX8QX,y)
171$(call force,CFG_ARM64_core,y)
172CFG_IMX_LPUART ?= y
173CFG_DRAM_BASE ?= 0x80000000
174CFG_TEE_CORE_NB_CORE ?= 4
175$(call force,CFG_NXP_CAAM,n)
176else
177$(error Unsupported PLATFORM_FLAVOR "$(PLATFORM_FLAVOR)")
178endif
179
180ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dsabresd))
181CFG_DDR_SIZE ?= 0x40000000
182CFG_NS_ENTRY_ADDR ?= 0x80800000
183endif
184
185ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dclsom))
186CFG_DDR_SIZE ?= 0x40000000
187CFG_UART_BASE ?= UART1_BASE
188endif
189
190ifneq (,$(filter $(PLATFORM_FLAVOR),mx7dpico_mbl))
191CFG_DDR_SIZE ?= 0x20000000
192CFG_NS_ENTRY_ADDR ?= 0x87800000
193CFG_DT_ADDR ?= 0x83100000
194CFG_UART_BASE ?= UART5_BASE
195CFG_BOOT_SECONDARY_REQUEST ?= n
196CFG_EXTERNAL_DTB_OVERLAY ?= y
197CFG_IMX_WDOG_EXT_RESET ?= y
198endif
199
200ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7))
201CFG_DDR_SIZE ?= 0x20000000
202CFG_NS_ENTRY_ADDR ?= 0x80800000
203CFG_BOOT_SECONDARY_REQUEST ?= n
204endif
205
206ifneq (,$(filter $(PLATFORM_FLAVOR),mx7swarp7_mbl))
207CFG_DDR_SIZE ?= 0x20000000
208CFG_NS_ENTRY_ADDR ?= 0x87800000
209CFG_DT_ADDR ?= 0x83100000
210CFG_BOOT_SECONDARY_REQUEST ?= n
211CFG_EXTERNAL_DTB_OVERLAY = y
212CFG_IMX_WDOG_EXT_RESET = y
213endif
214
215ifneq (,$(filter $(PLATFORM_FLAVOR),mx7ulpevk))
216CFG_DDR_SIZE ?= 0x40000000
217CFG_NS_ENTRY_ADDR ?= 0x60800000
218CFG_UART_BASE ?= UART4_BASE
219endif
220
221ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabresd mx6qsabresd mx6dlsabresd \
222	mx6dlsabrelite mx6dhmbedge mx6dlhmbedge mx6solosabresd \
223	mx6dapalis mx6qapalis))
224CFG_DDR_SIZE ?= 0x40000000
225CFG_NS_ENTRY_ADDR ?= 0x12000000
226endif
227
228ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qpsabreauto mx6qsabreauto \
229	mx6dlsabreauto mx6solosabreauto))
230CFG_DDR_SIZE ?= 0x80000000
231CFG_NS_ENTRY_ADDR ?= 0x12000000
232CFG_UART_BASE ?= UART4_BASE
233endif
234
235ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qhmbedge))
236CFG_DDR_SIZE ?= 0x80000000
237CFG_UART_BASE ?= UART1_BASE
238endif
239
240ifneq (,$(filter $(PLATFORM_FLAVOR),mx6shmbedge))
241CFG_DDR_SIZE ?= 0x40000000
242CFG_NS_ENTRY_ADDR ?= 0x12000000
243endif
244
245ifneq (,$(filter $(PLATFORM_FLAVOR),mx6qsabrelite mx6dlsabrelite))
246CFG_DDR_SIZE ?= 0x40000000
247CFG_NS_ENTRY_ADDR ?= 0x12000000
248CFG_UART_BASE ?= UART2_BASE
249endif
250
251ifneq (,$(filter $(PLATFORM_FLAVOR),mx6slevk))
252CFG_NS_ENTRY_ADDR ?= 0x80800000
253CFG_DDR_SIZE ?= 0x40000000
254endif
255
256ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sllevk))
257CFG_NS_ENTRY_ADDR ?= 0x80800000
258CFG_DDR_SIZE ?= 0x80000000
259endif
260
261ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabreauto))
262CFG_DDR_SIZE ?= 0x80000000
263CFG_NS_ENTRY_ADDR ?= 0x80800000
264endif
265
266ifneq (,$(filter $(PLATFORM_FLAVOR),mx6sxsabresd))
267CFG_DDR_SIZE ?= 0x40000000
268CFG_NS_ENTRY_ADDR ?= 0x80800000
269endif
270
271ifeq ($(PLATFORM_FLAVOR), mx6sxudooneofull)
272CFG_DDR_SIZE ?= 0x40000000
273CFG_UART_BASE ?= UART1_BASE
274endif
275
276ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulevk mx6ullevk mx6ulzevk))
277CFG_DDR_SIZE ?= 0x20000000
278CFG_NS_ENTRY_ADDR ?= 0x80800000
279endif
280
281ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ulccimx6ulsbcpro))
282CFG_DDR_SIZE ?= 0x10000000
283CFG_NS_ENTRY_ADDR ?= 0x80800000
284CFG_UART_BASE ?= UART5_BASE
285endif
286
287ifneq (,$(filter $(PLATFORM_FLAVOR),mx6ul9x9evk))
288CFG_DDR_SIZE ?= 0x10000000
289CFG_NS_ENTRY_ADDR ?= 0x80800000
290endif
291
292ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mqevk))
293CFG_DDR_SIZE ?= 0xc0000000
294CFG_UART_BASE ?= UART1_BASE
295endif
296
297ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mmevk))
298CFG_DDR_SIZE ?= 0x80000000
299CFG_UART_BASE ?= UART2_BASE
300endif
301
302ifneq (,$(filter $(PLATFORM_FLAVOR),mx8mnevk))
303CFG_DDR_SIZE ?= 0x80000000
304CFG_UART_BASE ?= UART2_BASE
305endif
306
307ifneq (,$(filter $(PLATFORM_FLAVOR),mx8qxpmek mx8qmmek))
308CFG_DDR_SIZE ?= 0x80000000
309CFG_UART_BASE ?= UART0_BASE
310CFG_NSEC_DDR_1_BASE ?= 0x880000000UL
311CFG_NSEC_DDR_1_SIZE  ?= 0x380000000UL
312CFG_CORE_ARM64_PA_BITS ?= 40
313endif
314
315# i.MX6 Solo/SL/SoloX/DualLite/Dual/Quad specific config
316ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S) \
317	$(CFG_MX6SL) $(CFG_MX6SLL) $(CFG_MX6SX)), y)
318include core/arch/arm/cpu/cortex-a9.mk
319
320$(call force,CFG_PL310,y)
321
322CFG_PL310_LOCKED ?= y
323CFG_ENABLE_SCTLR_RR ?= y
324CFG_SCU ?= y
325endif
326
327ifeq ($(filter y, $(CFG_MX6QP) $(CFG_MX6Q) $(CFG_MX6D) $(CFG_MX6DL) $(CFG_MX6S)), y)
328CFG_DRAM_BASE ?= 0x10000000
329endif
330
331ifneq (,$(filter y, $(CFG_MX6UL) $(CFG_MX6ULL) $(CFG_MX6SL) $(CFG_MX6SLL) \
332	$(CFG_MX6SX)))
333CFG_DRAM_BASE ?= 0x80000000
334endif
335
336ifeq ($(filter y, $(CFG_MX7)), y)
337CFG_INIT_CNTVOFF ?= y
338CFG_DRAM_BASE ?= 0x80000000
339endif
340
341ifeq ($(filter y, $(CFG_MX7ULP)), y)
342CFG_INIT_CNTVOFF ?= y
343CFG_DRAM_BASE ?= UL(0x60000000)
344$(call force,CFG_IMX_LPUART,y)
345$(call force,CFG_BOOT_SECONDARY_REQUEST,n)
346endif
347
348ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
349$(call force,CFG_GIC,y)
350$(call force,CFG_PM_STUBS,y)
351
352CFG_BOOT_SECONDARY_REQUEST ?= y
353CFG_DT ?= y
354CFG_PAGEABLE_ADDR ?= 0
355CFG_PSCI_ARM32 ?= y
356CFG_SECURE_TIME_SOURCE_REE ?= y
357CFG_UART_BASE ?= UART1_BASE
358endif
359
360ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7)))
361$(call force,CFG_IMX_UART,y)
362ifeq ($(CFG_RPMB_FS),y)
363CFG_IMX_SNVS ?= y
364endif
365CFG_CSU ?= y
366endif
367
368ifeq ($(filter y, $(CFG_PSCI_ARM32)), y)
369CFG_HWSUPP_MEM_PERM_WXN = n
370CFG_IMX_WDOG ?= y
371endif
372
373ifeq ($(CFG_ARM64_core),y)
374# arm-v8 platforms
375include core/arch/arm/cpu/cortex-armv8-0.mk
376$(call force,CFG_ARM_GICV3,y)
377$(call force,CFG_GIC,y)
378$(call force,CFG_WITH_LPAE,y)
379$(call force,CFG_WITH_ARM_TRUSTED_FW,y)
380$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y)
381
382CFG_CRYPTO_WITH_CE ?= y
383CFG_PM_STUBS ?= y
384
385supported-ta-targets = ta_arm64
386endif
387
388CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) - 0x02000000 + $(CFG_DDR_SIZE))
389CFG_TZDRAM_SIZE ?= 0x01e00000
390CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE))
391CFG_SHMEM_SIZE ?= 0x00200000
392
393CFG_NSEC_DDR_0_BASE ?= $(CFG_DRAM_BASE)
394CFG_NSEC_DDR_0_SIZE ?= ($(CFG_DDR_SIZE) - 0x02000000)
395
396CFG_CRYPTO_SIZE_OPTIMIZATION ?= n
397CFG_MMAP_REGIONS ?= 24
398
399# Almost all platforms include CAAM HW Modules, except the
400# ones forced to be disabled
401CFG_NXP_CAAM ?= n
402
403ifeq ($(CFG_NXP_CAAM),y)
404# As NXP CAAM Driver is enabled, disable the small local CAAM driver
405# used just to release Job Rings to Non-Secure world
406$(call force,CFG_IMX_CAAM,n)
407
408# If NXP CAAM Driver is supported, the Crypto Driver interfacing
409# it with generic crypto API can be enabled.
410CFG_CRYPTO_DRIVER ?= y
411# Crypto Driver Debug
412# DRV_DBG_TRACE BIT32(0) // Driver trace
413# DRV_DBG_BUF   BIT32(1) // Driver dump Buffer
414CFG_CRYPTO_DRIVER_DEBUG ?= 0
415else
416$(call force,CFG_CRYPTO_DRIVER,n)
417$(call force,CFG_WITH_SOFTWARE_PRNG,y)
418
419ifneq (,$(filter y, $(CFG_MX6) $(CFG_MX7) $(CFG_MX7ULP)))
420CFG_IMX_CAAM ?= y
421endif
422endif
423
424# Cryptographic configuration
425include core/arch/arm/plat-imx/crypto_conf.mk
426