1/* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Please keep them sorted based on the CRn register */ 29 30 .macro read_midr reg 31 mrc p15, 0, \reg, c0, c0, 0 32 .endm 33 34 .macro read_ctr reg 35 mrc p15, 0, \reg, c0, c0, 1 36 .endm 37 38 .macro read_mpidr reg 39 mrc p15, 0, \reg, c0, c0, 5 40 .endm 41 42 .macro read_sctlr reg 43 mrc p15, 0, \reg, c1, c0, 0 44 .endm 45 46 .macro write_sctlr reg 47 mcr p15, 0, \reg, c1, c0, 0 48 .endm 49 50 .macro write_actlr reg 51 mcr p15, 0, \reg, c1, c0, 1 52 .endm 53 54 .macro read_actlr reg 55 mrc p15, 0, \reg, c1, c0, 1 56 .endm 57 58 .macro write_cpacr reg 59 mcr p15, 0, \reg, c1, c0, 2 60 .endm 61 62 .macro read_cpacr reg 63 mrc p15, 0, \reg, c1, c0, 2 64 .endm 65 66 .macro read_scr reg 67 mrc p15, 0, \reg, c1, c1, 0 68 .endm 69 70 .macro write_scr reg 71 mcr p15, 0, \reg, c1, c1, 0 72 .endm 73 74 .macro write_nsacr reg 75 mcr p15, 0, \reg, c1, c1, 2 76 .endm 77 78 .macro read_nsacr reg 79 mrc p15, 0, \reg, c1, c1, 2 80 .endm 81 82 .macro write_ttbr0 reg 83 mcr p15, 0, \reg, c2, c0, 0 84 .endm 85 86 .macro write_ttbr0_64bit reg0, reg1 87 mcrr p15, 0, \reg0, \reg1, cr2 88 .endm 89 90 .macro read_ttbr0 reg 91 mrc p15, 0, \reg, c2, c0, 0 92 .endm 93 94 .macro read_ttbr0_64bit reg0, reg1 95 mrrc p15, 0, \reg0, \reg1, cr2 96 .endm 97 98 .macro write_ttbr1 reg 99 mcr p15, 0, \reg, c2, c0, 1 100 .endm 101 102 .macro read_ttbr1 reg 103 mrc p15, 0, \reg, c2, c0, 1 104 .endm 105 106 .macro write_ttbcr reg 107 mcr p15, 0, \reg, c2, c0, 2 108 .endm 109 110 .macro read_ttbcr reg 111 mrc p15, 0, \reg, c2, c0, 2 112 .endm 113 114 115 .macro write_dacr reg 116 mcr p15, 0, \reg, c3, c0, 0 117 .endm 118 119 .macro read_dacr reg 120 mrc p15, 0, \reg, c3, c0, 0 121 .endm 122 123 .macro read_dfsr reg 124 mrc p15, 0, \reg, c5, c0, 0 125 .endm 126 127 .macro write_icialluis 128 /* 129 * Invalidate all instruction caches to PoU, Inner Shareable 130 * (register ignored) 131 */ 132 mcr p15, 0, r0, c7, c1, 0 133 .endm 134 135 .macro write_bpiallis 136 /* 137 * Invalidate entire branch predictor array, Inner Shareable 138 * (register ignored) 139 */ 140 mcr p15, 0, r0, c7, c1, 6 141 .endm 142 143 .macro write_iciallu 144 /* Invalidate all instruction caches to PoU (register ignored) */ 145 mcr p15, 0, r0, c7, c5, 0 146 .endm 147 148 .macro write_icimvau reg 149 /* Instruction cache invalidate by MVA */ 150 mcr p15, 0, \reg, c7, c5, 1 151 .endm 152 153 .macro write_bpiall 154 /* Invalidate entire branch predictor array (register ignored) */ 155 mcr p15, 0, r0, c7, c5, 6 156 .endm 157 158 .macro write_dcimvac reg 159 /* Data cache invalidate by MVA */ 160 mcr p15, 0, \reg, c7, c6, 1 161 .endm 162 163 .macro write_dcisw reg 164 /* Data cache invalidate by set/way */ 165 mcr p15, 0, \reg, c7, c6, 2 166 .endm 167 168 .macro write_dccmvac reg 169 /* Data cache clean by MVA */ 170 mcr p15, 0, \reg, c7, c10, 1 171 .endm 172 173 .macro write_dccsw reg 174 /* Data cache clean by set/way */ 175 mcr p15, 0, \reg, c7, c10, 2 176 .endm 177 178 .macro write_dccimvac reg 179 /* Data cache invalidate by MVA */ 180 mcr p15, 0, \reg, c7, c14, 1 181 .endm 182 183 .macro write_dccisw reg 184 /* Data cache clean and invalidate by set/way */ 185 mcr p15, 0, \reg, c7, c14, 2 186 .endm 187 188 .macro write_tlbiall 189 /* Invalidate entire unified TLB (register ignored) */ 190 mcr p15, 0, r0, c8, c7, 0 191 .endm 192 193 .macro write_tlbiallis 194 /* Invalidate entire unified TLB Inner Sharable (register ignored) */ 195 mcr p15, 0, r0, c8, c3, 0 196 .endm 197 198 .macro write_tlbiasidis reg 199 /* Invalidate unified TLB by ASID Inner Sharable */ 200 mcr p15, 0, \reg, c8, c3, 2 201 .endm 202 203 .macro write_tlbimvaais reg 204 /* Invalidate unified TLB by MVA all ASID Inner Sharable */ 205 mcr p15, 0, \reg, c8, c3, 3 206 .endm 207 208 .macro write_prrr reg 209 mcr p15, 0, \reg, c10, c2, 0 210 .endm 211 212 .macro read_prrr reg 213 mrc p15, 0, \reg, c10, c2, 0 214 .endm 215 216 .macro write_nmrr reg 217 mcr p15, 0, \reg, c10, c2, 1 218 .endm 219 220 .macro read_nmrr reg 221 mrc p15, 0, \reg, c10, c2, 1 222 .endm 223 224 .macro read_vbar reg 225 mrc p15, 0, \reg, c12, c0, 0 226 .endm 227 228 .macro write_vbar reg 229 mcr p15, 0, \reg, c12, c0, 0 230 .endm 231 232 .macro write_mvbar reg 233 mcr p15, 0, \reg, c12, c0, 1 234 .endm 235 236 .macro read_mvbar reg 237 mrc p15, 0, \reg, c12, c0, 1 238 .endm 239 240 .macro write_fcseidr reg 241 mcr p15, 0, \reg, c13, c0, 0 242 .endm 243 244 .macro read_fcseidr reg 245 mrc p15, 0, \reg, c13, c0, 0 246 .endm 247 248 .macro write_contextidr reg 249 mcr p15, 0, \reg, c13, c0, 1 250 .endm 251 252 .macro read_contextidr reg 253 mrc p15, 0, \reg, c13, c0, 1 254 .endm 255 256 .macro write_tpidruro reg 257 mcr p15, 0, \reg, c13, c0, 3 258 .endm 259 260 .macro read_tpidruro reg 261 mrc p15, 0, \reg, c13, c0, 3 262 .endm 263 264 .macro write_tpidrprw reg 265 mcr p15, 0, \reg, c13, c0, 4 266 .endm 267 268 .macro read_tpidrprw reg 269 mrc p15, 0, \reg, c13, c0, 4 270 .endm 271 272 .macro read_clidr reg 273 /* Cache Level ID Register */ 274 mrc p15, 1, \reg, c0, c0, 1 275 .endm 276 277 .macro read_ccsidr reg 278 /* Cache Size ID Registers */ 279 mrc p15, 1, \reg, c0, c0, 0 280 .endm 281 282 .macro write_csselr reg 283 /* Cache Size Selection Register */ 284 mcr p15, 2, \reg, c0, c0, 0 285 .endm 286 287 .macro mov_imm reg, val 288 .if ((\val) & 0xffff0000) == 0 289 movw \reg, #(\val) 290 .else 291 movw \reg, #((\val) & 0xffff) 292 movt \reg, #((\val) >> 16) 293 .endif 294 .endm 295 296