1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* Please keep them sorted based on the CRn register */ 30 31 .macro read_midr reg 32 mrc p15, 0, \reg, c0, c0, 0 33 .endm 34 35 .macro read_ctr reg 36 mrc p15, 0, \reg, c0, c0, 1 37 .endm 38 39 .macro read_mpidr reg 40 mrc p15, 0, \reg, c0, c0, 5 41 .endm 42 43 .macro read_idpfr1 reg 44 mrc p15, 0, \reg, c0, c1, 1 45 .endm 46 47 .macro read_sctlr reg 48 mrc p15, 0, \reg, c1, c0, 0 49 .endm 50 51 .macro write_sctlr reg 52 mcr p15, 0, \reg, c1, c0, 0 53 .endm 54 55 .macro write_actlr reg 56 mcr p15, 0, \reg, c1, c0, 1 57 .endm 58 59 .macro read_actlr reg 60 mrc p15, 0, \reg, c1, c0, 1 61 .endm 62 63 .macro write_cpacr reg 64 mcr p15, 0, \reg, c1, c0, 2 65 .endm 66 67 .macro read_cpacr reg 68 mrc p15, 0, \reg, c1, c0, 2 69 .endm 70 71 .macro read_scr reg 72 mrc p15, 0, \reg, c1, c1, 0 73 .endm 74 75 .macro write_scr reg 76 mcr p15, 0, \reg, c1, c1, 0 77 .endm 78 79 .macro write_nsacr reg 80 mcr p15, 0, \reg, c1, c1, 2 81 .endm 82 83 .macro read_nsacr reg 84 mrc p15, 0, \reg, c1, c1, 2 85 .endm 86 87 .macro write_ttbr0 reg 88 mcr p15, 0, \reg, c2, c0, 0 89 .endm 90 91 .macro write_ttbr0_64bit reg0, reg1 92 mcrr p15, 0, \reg0, \reg1, cr2 93 .endm 94 95 .macro read_ttbr0 reg 96 mrc p15, 0, \reg, c2, c0, 0 97 .endm 98 99 .macro read_ttbr0_64bit reg0, reg1 100 mrrc p15, 0, \reg0, \reg1, cr2 101 .endm 102 103 .macro write_ttbr1 reg 104 mcr p15, 0, \reg, c2, c0, 1 105 .endm 106 107 .macro read_ttbr1 reg 108 mrc p15, 0, \reg, c2, c0, 1 109 .endm 110 111 .macro write_ttbcr reg 112 mcr p15, 0, \reg, c2, c0, 2 113 .endm 114 115 .macro read_ttbcr reg 116 mrc p15, 0, \reg, c2, c0, 2 117 .endm 118 119 120 .macro write_dacr reg 121 mcr p15, 0, \reg, c3, c0, 0 122 .endm 123 124 .macro read_dacr reg 125 mrc p15, 0, \reg, c3, c0, 0 126 .endm 127 128 .macro read_dfsr reg 129 mrc p15, 0, \reg, c5, c0, 0 130 .endm 131 132 .macro write_icialluis 133 /* 134 * Invalidate all instruction caches to PoU, Inner Shareable 135 * (register ignored) 136 */ 137 mcr p15, 0, r0, c7, c1, 0 138 .endm 139 140 .macro write_bpiallis 141 /* 142 * Invalidate entire branch predictor array, Inner Shareable 143 * (register ignored) 144 */ 145 mcr p15, 0, r0, c7, c1, 6 146 .endm 147 148 .macro write_iciallu 149 /* Invalidate all instruction caches to PoU (register ignored) */ 150 mcr p15, 0, r0, c7, c5, 0 151 .endm 152 153 .macro write_icimvau reg 154 /* Instruction cache invalidate by MVA */ 155 mcr p15, 0, \reg, c7, c5, 1 156 .endm 157 158 .macro write_bpiall 159 /* Invalidate entire branch predictor array (register ignored) */ 160 mcr p15, 0, r0, c7, c5, 6 161 .endm 162 163 .macro write_dcimvac reg 164 /* Data cache invalidate by MVA */ 165 mcr p15, 0, \reg, c7, c6, 1 166 .endm 167 168 .macro write_dcisw reg 169 /* Data cache invalidate by set/way */ 170 mcr p15, 0, \reg, c7, c6, 2 171 .endm 172 173 .macro write_dccmvac reg 174 /* Data cache clean by MVA */ 175 mcr p15, 0, \reg, c7, c10, 1 176 .endm 177 178 .macro write_dccsw reg 179 /* Data cache clean by set/way */ 180 mcr p15, 0, \reg, c7, c10, 2 181 .endm 182 183 .macro write_dccimvac reg 184 /* Data cache invalidate by MVA */ 185 mcr p15, 0, \reg, c7, c14, 1 186 .endm 187 188 .macro write_dccisw reg 189 /* Data cache clean and invalidate by set/way */ 190 mcr p15, 0, \reg, c7, c14, 2 191 .endm 192 193 .macro write_tlbiall 194 /* Invalidate entire unified TLB (register ignored) */ 195 mcr p15, 0, r0, c8, c7, 0 196 .endm 197 198 .macro write_tlbiallis 199 /* Invalidate entire unified TLB Inner Sharable (register ignored) */ 200 mcr p15, 0, r0, c8, c3, 0 201 .endm 202 203 .macro write_tlbiasidis reg 204 /* Invalidate unified TLB by ASID Inner Sharable */ 205 mcr p15, 0, \reg, c8, c3, 2 206 .endm 207 208 .macro write_tlbimvaais reg 209 /* Invalidate unified TLB by MVA all ASID Inner Sharable */ 210 mcr p15, 0, \reg, c8, c3, 3 211 .endm 212 213 .macro write_prrr reg 214 mcr p15, 0, \reg, c10, c2, 0 215 .endm 216 217 .macro read_prrr reg 218 mrc p15, 0, \reg, c10, c2, 0 219 .endm 220 221 .macro write_nmrr reg 222 mcr p15, 0, \reg, c10, c2, 1 223 .endm 224 225 .macro read_nmrr reg 226 mrc p15, 0, \reg, c10, c2, 1 227 .endm 228 229 .macro read_vbar reg 230 mrc p15, 0, \reg, c12, c0, 0 231 .endm 232 233 .macro write_vbar reg 234 mcr p15, 0, \reg, c12, c0, 0 235 .endm 236 237 .macro write_mvbar reg 238 mcr p15, 0, \reg, c12, c0, 1 239 .endm 240 241 .macro read_mvbar reg 242 mrc p15, 0, \reg, c12, c0, 1 243 .endm 244 245 .macro write_fcseidr reg 246 mcr p15, 0, \reg, c13, c0, 0 247 .endm 248 249 .macro read_fcseidr reg 250 mrc p15, 0, \reg, c13, c0, 0 251 .endm 252 253 .macro write_contextidr reg 254 mcr p15, 0, \reg, c13, c0, 1 255 .endm 256 257 .macro read_contextidr reg 258 mrc p15, 0, \reg, c13, c0, 1 259 .endm 260 261 .macro write_tpidruro reg 262 mcr p15, 0, \reg, c13, c0, 3 263 .endm 264 265 .macro read_tpidruro reg 266 mrc p15, 0, \reg, c13, c0, 3 267 .endm 268 269 .macro write_tpidrprw reg 270 mcr p15, 0, \reg, c13, c0, 4 271 .endm 272 273 .macro read_tpidrprw reg 274 mrc p15, 0, \reg, c13, c0, 4 275 .endm 276 277 .macro write_cntvoff reg0, reg1 278 mcrr p15, 4, \reg0, \reg1, c14 279 .endm 280 281 .macro read_clidr reg 282 /* Cache Level ID Register */ 283 mrc p15, 1, \reg, c0, c0, 1 284 .endm 285 286 .macro read_ccsidr reg 287 /* Cache Size ID Registers */ 288 mrc p15, 1, \reg, c0, c0, 0 289 .endm 290 291 .macro write_csselr reg 292 /* Cache Size Selection Register */ 293 mcr p15, 2, \reg, c0, c0, 0 294 .endm 295 296 .macro mov_imm reg, val 297 .if ((\val) & 0xffff0000) == 0 298 movw \reg, #(\val) 299 .else 300 movw \reg, #((\val) & 0xffff) 301 movt \reg, #((\val) >> 16) 302 .endif 303 .endm 304 305