1/* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 /* Please keep them sorted based on the CRn register */ 29 30 .macro read_midr reg 31 mrc p15, 0, \reg, c0, c0, 0 32 .endm 33 34 .macro read_ctr reg 35 mrc p15, 0, \reg, c0, c0, 1 36 .endm 37 38 .macro read_mpidr reg 39 mrc p15, 0, \reg, c0, c0, 5 40 .endm 41 42 .macro read_sctlr reg 43 mrc p15, 0, \reg, c1, c0, 0 44 .endm 45 46 .macro write_sctlr reg 47 mcr p15, 0, \reg, c1, c0, 0 48 .endm 49 50 .macro write_actlr reg 51 mcr p15, 0, \reg, c1, c0, 1 52 .endm 53 54 .macro read_actlr reg 55 mrc p15, 0, \reg, c1, c0, 1 56 .endm 57 58 .macro write_cpacr reg 59 mcr p15, 0, \reg, c1, c0, 2 60 .endm 61 62 .macro read_cpacr reg 63 mrc p15, 0, \reg, c1, c0, 2 64 .endm 65 66 .macro read_scr reg 67 mrc p15, 0, \reg, c1, c1, 0 68 .endm 69 70 .macro write_scr reg 71 mcr p15, 0, \reg, c1, c1, 0 72 .endm 73 74 .macro write_nsacr reg 75 mcr p15, 0, \reg, c1, c1, 2 76 .endm 77 78 .macro read_nsacr reg 79 mrc p15, 0, \reg, c1, c1, 2 80 .endm 81 82 .macro write_ttbr0 reg 83 mcr p15, 0, \reg, c2, c0, 0 84 .endm 85 86 .macro read_ttbr0 reg 87 mrc p15, 0, \reg, c2, c0, 0 88 .endm 89 90 .macro write_ttbr1 reg 91 mcr p15, 0, \reg, c2, c0, 1 92 .endm 93 94 .macro read_ttbr1 reg 95 mrc p15, 0, \reg, c2, c0, 1 96 .endm 97 98 .macro write_ttbcr reg 99 mcr p15, 0, \reg, c2, c0, 2 100 .endm 101 102 .macro read_ttbcr reg 103 mrc p15, 0, \reg, c2, c0, 2 104 .endm 105 106 107 .macro write_dacr reg 108 mcr p15, 0, \reg, c3, c0, 0 109 .endm 110 111 .macro read_dacr reg 112 mrc p15, 0, \reg, c3, c0, 0 113 .endm 114 115 .macro read_dfsr reg 116 mrc p15, 0, \reg, c5, c0, 0 117 .endm 118 119 .macro write_icialluis 120 /* 121 * Invalidate all instruction caches to PoU, Inner Shareable 122 * (register ignored) 123 */ 124 mcr p15, 0, r0, c7, c1, 0 125 .endm 126 127 .macro write_bpiallis 128 /* 129 * Invalidate entire branch predictor array, Inner Shareable 130 * (register ignored) 131 */ 132 mcr p15, 0, r0, c7, c1, 6 133 .endm 134 135 .macro write_iciallu 136 /* Invalidate all instruction caches to PoU (register ignored) */ 137 mcr p15, 0, r0, c7, c5, 0 138 .endm 139 140 .macro write_icimvau reg 141 /* Instruction cache invalidate by MVA */ 142 mcr p15, 0, \reg, c7, c5, 1 143 .endm 144 145 .macro write_bpiall 146 /* Invalidate entire branch predictor array (register ignored) */ 147 mcr p15, 0, r0, c7, c5, 6 148 .endm 149 150 .macro write_dcimvac reg 151 /* Data cache invalidate by MVA */ 152 mcr p15, 0, \reg, c7, c6, 1 153 .endm 154 155 .macro write_dcisw reg 156 /* Data cache invalidate by set/way */ 157 mcr p15, 0, \reg, c7, c6, 2 158 .endm 159 160 .macro write_dccmvac reg 161 /* Data cache clean by MVA */ 162 mcr p15, 0, \reg, c7, c10, 1 163 .endm 164 165 .macro write_dccsw reg 166 /* Data cache clean by set/way */ 167 mcr p15, 0, \reg, c7, c10, 2 168 .endm 169 170 .macro write_dccimvac reg 171 /* Data cache invalidate by MVA */ 172 mcr p15, 0, \reg, c7, c14, 1 173 .endm 174 175 .macro write_dccisw reg 176 /* Data cache clean and invalidate by set/way */ 177 mcr p15, 0, \reg, c7, c14, 2 178 .endm 179 180 .macro write_tlbiall 181 /* Invalidate entire unified TLB (register ignored) */ 182 mcr p15, 0, r0, c8, c7, 0 183 .endm 184 185 .macro write_tlbiallis 186 /* Invalidate entire unified TLB Inner Sharable (register ignored) */ 187 mcr p15, 0, r0, c8, c3, 0 188 .endm 189 190 .macro write_tlbiasidis reg 191 /* Invalidate unified TLB by ASID Inner Sharable */ 192 mcr p15, 0, \reg, c8, c3, 2 193 .endm 194 195 .macro write_tlbimvaais reg 196 /* Invalidate unified TLB by MVA all ASID Inner Sharable */ 197 mcr p15, 0, \reg, c8, c3, 3 198 .endm 199 200 .macro write_prrr reg 201 mcr p15, 0, \reg, c10, c2, 0 202 .endm 203 204 .macro read_prrr reg 205 mrc p15, 0, \reg, c10, c2, 0 206 .endm 207 208 .macro write_nmrr reg 209 mcr p15, 0, \reg, c10, c2, 1 210 .endm 211 212 .macro read_nmrr reg 213 mrc p15, 0, \reg, c10, c2, 1 214 .endm 215 216 .macro read_vbar reg 217 mrc p15, 0, \reg, c12, c0, 0 218 .endm 219 220 .macro write_vbar reg 221 mcr p15, 0, \reg, c12, c0, 0 222 .endm 223 224 .macro write_mvbar reg 225 mcr p15, 0, \reg, c12, c0, 1 226 .endm 227 228 .macro read_mvbar reg 229 mrc p15, 0, \reg, c12, c0, 1 230 .endm 231 232 .macro write_fcseidr reg 233 mcr p15, 0, \reg, c13, c0, 0 234 .endm 235 236 .macro read_fcseidr reg 237 mrc p15, 0, \reg, c13, c0, 0 238 .endm 239 240 .macro write_contextidr reg 241 mcr p15, 0, \reg, c13, c0, 1 242 .endm 243 244 .macro read_contextidr reg 245 mrc p15, 0, \reg, c13, c0, 1 246 .endm 247 248 .macro write_tpidruro reg 249 mcr p15, 0, \reg, c13, c0, 3 250 .endm 251 252 .macro read_tpidruro reg 253 mrc p15, 0, \reg, c13, c0, 3 254 .endm 255 256 .macro read_clidr reg 257 /* Cache Level ID Register */ 258 mrc p15, 1, \reg, c0, c0, 1 259 .endm 260 261 .macro read_ccsidr reg 262 /* Cache Size ID Registers */ 263 mrc p15, 1, \reg, c0, c0, 0 264 .endm 265 266 .macro write_csselr reg 267 /* Cache Size Selection Register */ 268 mcr p15, 2, \reg, c0, c0, 0 269 .endm 270 271 .macro mov_imm reg, val 272 .if ((\val) & 0xffff0000) == 0 273 movw \reg, #(\val) 274 .else 275 movw \reg, #((\val) & 0xffff) 276 movt \reg, #((\val) >> 16) 277 .endif 278 .endm 279 280