1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 */ 5 6 /* Please keep them sorted based on the CRn register */ 7 8 .macro read_midr reg 9 mrc p15, 0, \reg, c0, c0, 0 10 .endm 11 12 .macro read_ctr reg 13 mrc p15, 0, \reg, c0, c0, 1 14 .endm 15 16 .macro read_mpidr reg 17 mrc p15, 0, \reg, c0, c0, 5 18 .endm 19 20 .macro read_idpfr1 reg 21 mrc p15, 0, \reg, c0, c1, 1 22 .endm 23 24 .macro read_sctlr reg 25 mrc p15, 0, \reg, c1, c0, 0 26 .endm 27 28 .macro write_sctlr reg 29 mcr p15, 0, \reg, c1, c0, 0 30 .endm 31 32 .macro write_actlr reg 33 mcr p15, 0, \reg, c1, c0, 1 34 .endm 35 36 .macro read_actlr reg 37 mrc p15, 0, \reg, c1, c0, 1 38 .endm 39 40 .macro write_cpacr reg 41 mcr p15, 0, \reg, c1, c0, 2 42 .endm 43 44 .macro read_cpacr reg 45 mrc p15, 0, \reg, c1, c0, 2 46 .endm 47 48 .macro read_scr reg 49 mrc p15, 0, \reg, c1, c1, 0 50 .endm 51 52 .macro write_scr reg 53 mcr p15, 0, \reg, c1, c1, 0 54 .endm 55 56 .macro write_nsacr reg 57 mcr p15, 0, \reg, c1, c1, 2 58 .endm 59 60 .macro read_nsacr reg 61 mrc p15, 0, \reg, c1, c1, 2 62 .endm 63 64 .macro write_ttbr0 reg 65 mcr p15, 0, \reg, c2, c0, 0 66 .endm 67 68 .macro write_ttbr0_64bit reg0, reg1 69 mcrr p15, 0, \reg0, \reg1, cr2 70 .endm 71 72 .macro read_ttbr0 reg 73 mrc p15, 0, \reg, c2, c0, 0 74 .endm 75 76 .macro read_ttbr0_64bit reg0, reg1 77 mrrc p15, 0, \reg0, \reg1, cr2 78 .endm 79 80 .macro write_ttbr1 reg 81 mcr p15, 0, \reg, c2, c0, 1 82 .endm 83 84 .macro read_ttbr1 reg 85 mrc p15, 0, \reg, c2, c0, 1 86 .endm 87 88 .macro write_ttbcr reg 89 mcr p15, 0, \reg, c2, c0, 2 90 .endm 91 92 .macro read_ttbcr reg 93 mrc p15, 0, \reg, c2, c0, 2 94 .endm 95 96 97 .macro write_dacr reg 98 mcr p15, 0, \reg, c3, c0, 0 99 .endm 100 101 .macro read_dacr reg 102 mrc p15, 0, \reg, c3, c0, 0 103 .endm 104 105 .macro read_dfsr reg 106 mrc p15, 0, \reg, c5, c0, 0 107 .endm 108 109 .macro write_icialluis 110 /* 111 * Invalidate all instruction caches to PoU, Inner Shareable 112 * (register ignored) 113 */ 114 mcr p15, 0, r0, c7, c1, 0 115 .endm 116 117 .macro write_bpiallis 118 /* 119 * Invalidate entire branch predictor array, Inner Shareable 120 * (register ignored) 121 */ 122 mcr p15, 0, r0, c7, c1, 6 123 .endm 124 125 .macro write_iciallu 126 /* Invalidate all instruction caches to PoU (register ignored) */ 127 mcr p15, 0, r0, c7, c5, 0 128 .endm 129 130 .macro write_icimvau reg 131 /* Instruction cache invalidate by MVA */ 132 mcr p15, 0, \reg, c7, c5, 1 133 .endm 134 135 .macro write_bpiall 136 /* Invalidate entire branch predictor array (register ignored) */ 137 mcr p15, 0, r0, c7, c5, 6 138 .endm 139 140 .macro write_dcimvac reg 141 /* Data cache invalidate by MVA */ 142 mcr p15, 0, \reg, c7, c6, 1 143 .endm 144 145 .macro write_dcisw reg 146 /* Data cache invalidate by set/way */ 147 mcr p15, 0, \reg, c7, c6, 2 148 .endm 149 150 .macro write_dccmvac reg 151 /* Data cache clean by MVA */ 152 mcr p15, 0, \reg, c7, c10, 1 153 .endm 154 155 .macro write_dccsw reg 156 /* Data cache clean by set/way */ 157 mcr p15, 0, \reg, c7, c10, 2 158 .endm 159 160 .macro write_dccimvac reg 161 /* Data cache invalidate by MVA */ 162 mcr p15, 0, \reg, c7, c14, 1 163 .endm 164 165 .macro write_dccisw reg 166 /* Data cache clean and invalidate by set/way */ 167 mcr p15, 0, \reg, c7, c14, 2 168 .endm 169 170 .macro write_tlbiall 171 /* Invalidate entire unified TLB (register ignored) */ 172 mcr p15, 0, r0, c8, c7, 0 173 .endm 174 175 .macro write_tlbiallis 176 /* Invalidate entire unified TLB Inner Sharable (register ignored) */ 177 mcr p15, 0, r0, c8, c3, 0 178 .endm 179 180 .macro write_tlbiasidis reg 181 /* Invalidate unified TLB by ASID Inner Sharable */ 182 mcr p15, 0, \reg, c8, c3, 2 183 .endm 184 185 .macro write_tlbimvaais reg 186 /* Invalidate unified TLB by MVA all ASID Inner Sharable */ 187 mcr p15, 0, \reg, c8, c3, 3 188 .endm 189 190 .macro write_prrr reg 191 mcr p15, 0, \reg, c10, c2, 0 192 .endm 193 194 .macro read_prrr reg 195 mrc p15, 0, \reg, c10, c2, 0 196 .endm 197 198 .macro write_nmrr reg 199 mcr p15, 0, \reg, c10, c2, 1 200 .endm 201 202 .macro read_nmrr reg 203 mrc p15, 0, \reg, c10, c2, 1 204 .endm 205 206 .macro read_vbar reg 207 mrc p15, 0, \reg, c12, c0, 0 208 .endm 209 210 .macro write_vbar reg 211 mcr p15, 0, \reg, c12, c0, 0 212 .endm 213 214 .macro write_mvbar reg 215 mcr p15, 0, \reg, c12, c0, 1 216 .endm 217 218 .macro read_mvbar reg 219 mrc p15, 0, \reg, c12, c0, 1 220 .endm 221 222 .macro write_fcseidr reg 223 mcr p15, 0, \reg, c13, c0, 0 224 .endm 225 226 .macro read_fcseidr reg 227 mrc p15, 0, \reg, c13, c0, 0 228 .endm 229 230 .macro write_contextidr reg 231 mcr p15, 0, \reg, c13, c0, 1 232 .endm 233 234 .macro read_contextidr reg 235 mrc p15, 0, \reg, c13, c0, 1 236 .endm 237 238 .macro write_tpidruro reg 239 mcr p15, 0, \reg, c13, c0, 3 240 .endm 241 242 .macro read_tpidruro reg 243 mrc p15, 0, \reg, c13, c0, 3 244 .endm 245 246 .macro write_tpidrprw reg 247 mcr p15, 0, \reg, c13, c0, 4 248 .endm 249 250 .macro read_tpidrprw reg 251 mrc p15, 0, \reg, c13, c0, 4 252 .endm 253 254 .macro write_cntvoff reg0, reg1 255 mcrr p15, 4, \reg0, \reg1, c14 256 .endm 257 258 .macro read_clidr reg 259 /* Cache Level ID Register */ 260 mrc p15, 1, \reg, c0, c0, 1 261 .endm 262 263 .macro read_ccsidr reg 264 /* Cache Size ID Registers */ 265 mrc p15, 1, \reg, c0, c0, 0 266 .endm 267 268 .macro write_csselr reg 269 /* Cache Size Selection Register */ 270 mcr p15, 2, \reg, c0, c0, 0 271 .endm 272 273 .macro mov_imm reg, val 274 .if ((\val) & 0xffff0000) == 0 275 movw \reg, #(\val) 276 .else 277 movw \reg, #((\val) & 0xffff) 278 movt \reg, #((\val) >> 16) 279 .endif 280 .endm 281 282