1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef ARM_H 28 #define ARM_H 29 30 31 #define MPIDR_CPU_MASK 0xff 32 #define MPIDR_CLUSTER_SHIFT 8 33 #define MPIDR_CLUSTER_MASK (0xff << MPIDR_CLUSTER_SHIFT) 34 35 36 /* CLIDR definitions */ 37 #define CLIDR_LOUIS_SHIFT 21 38 #define CLIDR_LOC_SHIFT 24 39 #define CLIDR_FIELD_WIDTH 3 40 41 /* CSSELR definitions */ 42 #define CSSELR_LEVEL_SHIFT 1 43 44 /* CTR definitions */ 45 #define CTR_CWG_SHIFT 24 46 #define CTR_CWG_MASK 0xf 47 #define CTR_ERG_SHIFT 20 48 #define CTR_ERG_MASK 0xf 49 #define CTR_DMINLINE_SHIFT 16 50 #define CTR_DMINLINE_WIDTH 4 51 #define CTR_DMINLINE_MASK ((1 << 4) - 1) 52 #define CTR_L1IP_SHIFT 14 53 #define CTR_L1IP_MASK 0x3 54 #define CTR_IMINLINE_SHIFT 0 55 #define CTR_IMINLINE_MASK 0xf 56 57 #define ARM32_CPSR_MODE_MASK 0x1f 58 #define ARM32_CPSR_MODE_USR 0x10 59 #define ARM32_CPSR_MODE_FIQ 0x11 60 #define ARM32_CPSR_MODE_IRQ 0x12 61 #define ARM32_CPSR_MODE_SVC 0x13 62 #define ARM32_CPSR_MODE_MON 0x16 63 #define ARM32_CPSR_MODE_ABT 0x17 64 #define ARM32_CPSR_MODE_UND 0x1b 65 #define ARM32_CPSR_MODE_SYS 0x1f 66 67 #define ARM32_CPSR_T (1 << 5) 68 #define ARM32_CPSR_F_SHIFT 6 69 #define ARM32_CPSR_F (1 << 6) 70 #define ARM32_CPSR_I (1 << 7) 71 #define ARM32_CPSR_A (1 << 8) 72 #define ARM32_CPSR_E (1 << 9) 73 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 74 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 75 #define ARM32_CPSR_IT_MASK1 0x06000000 76 #define ARM32_CPSR_IT_MASK2 0x0000fc00 77 78 79 #ifdef ARM32 80 #include <arm32.h> 81 #endif 82 83 #ifdef ARM64 84 #include <arm64.h> 85 #endif 86 87 #endif /*ARM_H*/ 88