1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * Copyright (c) 2019-2023, Arm Limited. All rights reserved. 5 */ 6 #ifndef __ARM_H 7 #define __ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 #include <util.h> 12 13 /* MIDR definitions */ 14 #define MIDR_PRIMARY_PART_NUM_SHIFT U(4) 15 #define MIDR_PRIMARY_PART_NUM_WIDTH U(12) 16 #define MIDR_PRIMARY_PART_NUM_MASK (BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1) 17 18 #define MIDR_IMPLEMENTER_SHIFT U(24) 19 #define MIDR_IMPLEMENTER_WIDTH U(8) 20 #define MIDR_IMPLEMENTER_MASK (BIT(MIDR_IMPLEMENTER_WIDTH) - 1) 21 #define MIDR_IMPLEMENTER_ARM U(0x41) 22 23 #define MIDR_VARIANT_SHIFT U(20) 24 #define MIDR_VARIANT_WIDTH U(4) 25 #define MIDR_VARIANT_MASK (BIT(MIDR_VARIANT_WIDTH) - 1) 26 27 #define MIDR_REVISION_SHIFT U(0) 28 #define MIDR_REVISION_WIDTH U(4) 29 #define MIDR_REVISION_MASK (BIT(MIDR_REVISION_WIDTH) - 1) 30 31 #define CORTEX_A5_PART_NUM U(0xC05) 32 #define CORTEX_A7_PART_NUM U(0xC07) 33 #define CORTEX_A8_PART_NUM U(0xC08) 34 #define CORTEX_A9_PART_NUM U(0xC09) 35 #define CORTEX_A15_PART_NUM U(0xC0F) 36 #define CORTEX_A17_PART_NUM U(0xC0E) 37 #define CORTEX_A57_PART_NUM U(0xD07) 38 #define CORTEX_A72_PART_NUM U(0xD08) 39 #define CORTEX_A73_PART_NUM U(0xD09) 40 #define CORTEX_A75_PART_NUM U(0xD0A) 41 #define CORTEX_A65_PART_NUM U(0xD06) 42 #define CORTEX_A65AE_PART_NUM U(0xD43) 43 #define CORTEX_A76_PART_NUM U(0xD0B) 44 #define CORTEX_A76AE_PART_NUM U(0xD0E) 45 #define CORTEX_A77_PART_NUM U(0xD0D) 46 #define CORTEX_A78_PART_NUM U(0xD41) 47 #define CORTEX_A78AE_PART_NUM U(0xD42) 48 #define CORTEX_A78C_PART_NUM U(0xD4B) 49 #define CORTEX_A710_PART_NUM U(0xD47) 50 #define CORTEX_X1_PART_NUM U(0xD44) 51 #define CORTEX_X2_PART_NUM U(0xD48) 52 #define NEOVERSE_E1_PART_NUM U(0xD4A) 53 #define NEOVERSE_N1_PART_NUM U(0xD0C) 54 #define NEOVERSE_N2_PART_NUM U(0xD49) 55 #define NEOVERSE_V1_PART_NUM U(0xD40) 56 57 /* MPIDR definitions */ 58 #define MPIDR_AFFINITY_BITS U(8) 59 #define MPIDR_AFFLVL_MASK ULL(0xff) 60 #define MPIDR_AFF0_SHIFT U(0) 61 #define MPIDR_AFF0_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT) 62 #define MPIDR_AFF1_SHIFT U(8) 63 #define MPIDR_AFF1_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) 64 #define MPIDR_AFF2_SHIFT U(16) 65 #define MPIDR_AFF2_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) 66 #define MPIDR_AFF3_SHIFT U(32) 67 #define MPIDR_AFF3_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) 68 69 #define MPIDR_MT_SHIFT U(24) 70 #define MPIDR_MT_MASK BIT(MPIDR_MT_SHIFT) 71 72 #define MPIDR_CPU_MASK MPIDR_AFF0_MASK 73 #define MPIDR_CLUSTER_SHIFT MPIDR_AFF1_SHIFT 74 #define MPIDR_CLUSTER_MASK MPIDR_AFF1_MASK 75 76 #define MPIDR_AARCH32_AFF_MASK (MPIDR_AFF0_MASK | MPIDR_AFF1_MASK | \ 77 MPIDR_AFF2_MASK) 78 79 /* CLIDR definitions */ 80 #define CLIDR_LOUIS_SHIFT U(21) 81 #define CLIDR_LOC_SHIFT U(24) 82 #define CLIDR_FIELD_WIDTH U(3) 83 84 /* CSSELR definitions */ 85 #define CSSELR_LEVEL_SHIFT U(1) 86 87 /* CTR definitions */ 88 #define CTR_CWG_SHIFT U(24) 89 #define CTR_CWG_MASK U(0xf) 90 #define CTR_ERG_SHIFT U(20) 91 #define CTR_ERG_MASK U(0xf) 92 #define CTR_DMINLINE_SHIFT U(16) 93 #define CTR_DMINLINE_WIDTH U(4) 94 #define CTR_DMINLINE_MASK (BIT(4) - 1) 95 #define CTR_L1IP_SHIFT U(14) 96 #define CTR_L1IP_MASK U(0x3) 97 #define CTR_IMINLINE_SHIFT U(0) 98 #define CTR_IMINLINE_MASK U(0xf) 99 #define CTR_WORD_SIZE U(4) 100 101 #define ARM32_CPSR_MODE_MASK U(0x1f) 102 #define ARM32_CPSR_MODE_USR U(0x10) 103 #define ARM32_CPSR_MODE_FIQ U(0x11) 104 #define ARM32_CPSR_MODE_IRQ U(0x12) 105 #define ARM32_CPSR_MODE_SVC U(0x13) 106 #define ARM32_CPSR_MODE_MON U(0x16) 107 #define ARM32_CPSR_MODE_ABT U(0x17) 108 #define ARM32_CPSR_MODE_UND U(0x1b) 109 #define ARM32_CPSR_MODE_SYS U(0x1f) 110 111 #define ARM32_CPSR_T BIT(5) 112 #define ARM32_CPSR_F_SHIFT U(6) 113 #define ARM32_CPSR_F BIT(6) 114 #define ARM32_CPSR_I BIT(7) 115 #define ARM32_CPSR_A BIT(8) 116 #define ARM32_CPSR_E BIT(9) 117 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 118 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 119 #define ARM32_CPSR_IT_MASK1 U(0x06000000) 120 #define ARM32_CPSR_IT_MASK2 U(0x0000fc00) 121 122 /* ARM Generic timer definitions */ 123 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 124 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 125 126 #ifdef ARM32 127 #include <arm32.h> 128 #endif 129 130 #ifdef ARM64 131 #include <arm64.h> 132 #endif 133 134 #ifndef __ASSEMBLER__ 135 static inline __noprof uint64_t barrier_read_counter_timer(void) 136 { 137 isb(); 138 #ifdef CFG_CORE_SEL2_SPMC 139 return read_cntvct(); 140 #else 141 return read_cntpct(); 142 #endif 143 } 144 145 static inline bool feat_bti_is_implemented(void) 146 { 147 #ifdef ARM32 148 return false; 149 #else 150 return ((read_id_aa64pfr1_el1() & ID_AA64PFR1_EL1_BT_MASK) == 151 FEAT_BTI_IMPLEMENTED); 152 #endif 153 } 154 155 static inline unsigned int feat_mte_implemented(void) 156 { 157 #ifdef ARM32 158 return 0; 159 #else 160 return (read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_MTE_SHIFT) & 161 ID_AA64PFR1_EL1_MTE_MASK; 162 #endif 163 } 164 165 static inline unsigned int feat_pan_implemented(void) 166 { 167 #ifdef ARM32 168 return 0; 169 #else 170 return (read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_PAN_SHIFT) & 171 ID_AA64MMFR1_EL1_PAN_MASK; 172 #endif 173 } 174 175 static inline bool feat_crc32_implemented(void) 176 { 177 #ifdef ARM32 178 return false; 179 #else 180 return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_EL1_CRC32_SHIFT) & 181 ID_AA64ISAR0_EL1_CRC32_MASK) == FEAT_CRC32_IMPLEMENTED; 182 #endif 183 } 184 185 static inline bool feat_pauth_is_implemented(void) 186 { 187 #ifdef ARM32 188 return false; 189 #else 190 uint64_t mask = 191 SHIFT_U64(ID_AA64ISAR1_GPI_MASK, ID_AA64ISAR1_GPI_SHIFT) | 192 SHIFT_U64(ID_AA64ISAR1_GPA_MASK, ID_AA64ISAR1_GPA_SHIFT) | 193 SHIFT_U64(ID_AA64ISAR1_API_MASK, ID_AA64ISAR1_API_SHIFT) | 194 SHIFT_U64(ID_AA64ISAR1_APA_MASK, ID_AA64ISAR1_APA_SHIFT); 195 196 /* If any of the fields is not zero, PAuth is implemented by arch */ 197 return (read_id_aa64isar1_el1() & mask) != 0U; 198 #endif 199 } 200 201 #endif 202 203 #endif /*__ARM_H*/ 204