1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 */ 5 #ifndef ARM_H 6 #define ARM_H 7 8 #include <util.h> 9 10 /* MIDR definitions */ 11 #define MIDR_PRIMARY_PART_NUM_SHIFT 4 12 #define MIDR_PRIMARY_PART_NUM_WIDTH 12 13 14 #define MIDR_IMPLEMENTER_SHIFT 24 15 #define MIDR_IMPLEMENTER_WIDTH 8 16 #define MIDR_IMPLEMENTER_ARM 0x41 17 18 #define CORTEX_A7_PART_NUM 0xC07 19 #define CORTEX_A8_PART_NUM 0xC08 20 #define CORTEX_A9_PART_NUM 0xC09 21 #define CORTEX_A15_PART_NUM 0xC0F 22 #define CORTEX_A17_PART_NUM 0xC0E 23 #define CORTEX_A57_PART_NUM 0xD07 24 #define CORTEX_A72_PART_NUM 0xD08 25 #define CORTEX_A73_PART_NUM 0xD09 26 #define CORTEX_A75_PART_NUM 0xD0A 27 28 /* MPIDR definitions */ 29 #define MPIDR_CPU_MASK 0xff 30 #define MPIDR_CLUSTER_SHIFT 8 31 #define MPIDR_CLUSTER_MASK (0xff << MPIDR_CLUSTER_SHIFT) 32 33 /* CLIDR definitions */ 34 #define CLIDR_LOUIS_SHIFT 21 35 #define CLIDR_LOC_SHIFT 24 36 #define CLIDR_FIELD_WIDTH 3 37 38 /* CSSELR definitions */ 39 #define CSSELR_LEVEL_SHIFT 1 40 41 /* CTR definitions */ 42 #define CTR_CWG_SHIFT 24 43 #define CTR_CWG_MASK 0xf 44 #define CTR_ERG_SHIFT 20 45 #define CTR_ERG_MASK 0xf 46 #define CTR_DMINLINE_SHIFT 16 47 #define CTR_DMINLINE_WIDTH 4 48 #define CTR_DMINLINE_MASK ((1 << 4) - 1) 49 #define CTR_L1IP_SHIFT 14 50 #define CTR_L1IP_MASK 0x3 51 #define CTR_IMINLINE_SHIFT 0 52 #define CTR_IMINLINE_MASK 0xf 53 54 #define ARM32_CPSR_MODE_MASK 0x1f 55 #define ARM32_CPSR_MODE_USR 0x10 56 #define ARM32_CPSR_MODE_FIQ 0x11 57 #define ARM32_CPSR_MODE_IRQ 0x12 58 #define ARM32_CPSR_MODE_SVC 0x13 59 #define ARM32_CPSR_MODE_MON 0x16 60 #define ARM32_CPSR_MODE_ABT 0x17 61 #define ARM32_CPSR_MODE_UND 0x1b 62 #define ARM32_CPSR_MODE_SYS 0x1f 63 64 #define ARM32_CPSR_T (1 << 5) 65 #define ARM32_CPSR_F_SHIFT 6 66 #define ARM32_CPSR_F (1 << 6) 67 #define ARM32_CPSR_I (1 << 7) 68 #define ARM32_CPSR_A (1 << 8) 69 #define ARM32_CPSR_E (1 << 9) 70 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 71 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 72 #define ARM32_CPSR_IT_MASK1 0x06000000 73 #define ARM32_CPSR_IT_MASK2 0x0000fc00 74 75 /* ARM Generic timer definitions */ 76 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 77 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 78 79 #ifdef ARM32 80 #include <arm32.h> 81 #endif 82 83 #ifdef ARM64 84 #include <arm64.h> 85 #endif 86 87 #endif /*ARM_H*/ 88