1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * Copyright (c) 2019, Arm Limited. All rights reserved. 5 */ 6 #ifndef ARM_H 7 #define ARM_H 8 9 #include <stdint.h> 10 #include <util.h> 11 12 /* MIDR definitions */ 13 #define MIDR_PRIMARY_PART_NUM_SHIFT U(4) 14 #define MIDR_PRIMARY_PART_NUM_WIDTH U(12) 15 #define MIDR_PRIMARY_PART_NUM_MASK (BIT(MIDR_PRIMARY_PART_NUM_WIDTH) - 1) 16 17 #define MIDR_IMPLEMENTER_SHIFT U(24) 18 #define MIDR_IMPLEMENTER_WIDTH U(8) 19 #define MIDR_IMPLEMENTER_MASK (BIT(MIDR_IMPLEMENTER_WIDTH) - 1) 20 #define MIDR_IMPLEMENTER_ARM U(0x41) 21 22 #define CORTEX_A7_PART_NUM U(0xC07) 23 #define CORTEX_A8_PART_NUM U(0xC08) 24 #define CORTEX_A9_PART_NUM U(0xC09) 25 #define CORTEX_A15_PART_NUM U(0xC0F) 26 #define CORTEX_A17_PART_NUM U(0xC0E) 27 #define CORTEX_A57_PART_NUM U(0xD07) 28 #define CORTEX_A72_PART_NUM U(0xD08) 29 #define CORTEX_A73_PART_NUM U(0xD09) 30 #define CORTEX_A75_PART_NUM U(0xD0A) 31 32 /* MPIDR definitions */ 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK U(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF0_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT) 37 #define MPIDR_AFF1_SHIFT U(8) 38 #define MPIDR_AFF1_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) 39 #define MPIDR_AFF2_SHIFT U(16) 40 #define MPIDR_AFF2_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) 41 42 #define MPIDR_MT_SHIFT U(24) 43 #define MPIDR_MT_MASK BIT(MPIDR_MT_SHIFT) 44 45 #define MPIDR_CPU_MASK MPIDR_AFF0_MASK 46 #define MPIDR_CLUSTER_SHIFT MPIDR_AFF1_SHIFT 47 #define MPIDR_CLUSTER_MASK MPIDR_AFF1_MASK 48 49 #define MPIDR_AARCH32_AFF_MASK (MPIDR_AFF0_MASK | MPIDR_AFF1_MASK | \ 50 MPIDR_AFF2_MASK) 51 52 /* CLIDR definitions */ 53 #define CLIDR_LOUIS_SHIFT U(21) 54 #define CLIDR_LOC_SHIFT U(24) 55 #define CLIDR_FIELD_WIDTH U(3) 56 57 /* CSSELR definitions */ 58 #define CSSELR_LEVEL_SHIFT U(1) 59 60 /* CTR definitions */ 61 #define CTR_CWG_SHIFT U(24) 62 #define CTR_CWG_MASK U(0xf) 63 #define CTR_ERG_SHIFT U(20) 64 #define CTR_ERG_MASK U(0xf) 65 #define CTR_DMINLINE_SHIFT U(16) 66 #define CTR_DMINLINE_WIDTH U(4) 67 #define CTR_DMINLINE_MASK (BIT(4) - 1) 68 #define CTR_L1IP_SHIFT U(14) 69 #define CTR_L1IP_MASK U(0x3) 70 #define CTR_IMINLINE_SHIFT U(0) 71 #define CTR_IMINLINE_MASK U(0xf) 72 #define CTR_WORD_SIZE U(4) 73 74 #define ARM32_CPSR_MODE_MASK U(0x1f) 75 #define ARM32_CPSR_MODE_USR U(0x10) 76 #define ARM32_CPSR_MODE_FIQ U(0x11) 77 #define ARM32_CPSR_MODE_IRQ U(0x12) 78 #define ARM32_CPSR_MODE_SVC U(0x13) 79 #define ARM32_CPSR_MODE_MON U(0x16) 80 #define ARM32_CPSR_MODE_ABT U(0x17) 81 #define ARM32_CPSR_MODE_UND U(0x1b) 82 #define ARM32_CPSR_MODE_SYS U(0x1f) 83 84 #define ARM32_CPSR_T BIT(5) 85 #define ARM32_CPSR_F_SHIFT U(6) 86 #define ARM32_CPSR_F BIT(6) 87 #define ARM32_CPSR_I BIT(7) 88 #define ARM32_CPSR_A BIT(8) 89 #define ARM32_CPSR_E BIT(9) 90 #define ARM32_CPSR_FIA (ARM32_CPSR_F | ARM32_CPSR_I | ARM32_CPSR_A) 91 #define ARM32_CPSR_IT_MASK (ARM32_CPSR_IT_MASK1 | ARM32_CPSR_IT_MASK2) 92 #define ARM32_CPSR_IT_MASK1 U(0x06000000) 93 #define ARM32_CPSR_IT_MASK2 U(0x0000fc00) 94 95 /* ARM Generic timer definitions */ 96 #define CNTKCTL_PL0PCTEN BIT(0) /* physical counter el0 access enable */ 97 #define CNTKCTL_PL0VCTEN BIT(1) /* virtual counter el0 access enable */ 98 99 #ifdef ARM32 100 #include <arm32.h> 101 #endif 102 103 #ifdef ARM64 104 #include <arm64.h> 105 #endif 106 107 #ifndef __ASSEMBLER__ 108 static inline __noprof uint64_t barrier_read_counter_timer(void) 109 { 110 isb(); 111 #ifdef CFG_CORE_SEL2_SPMC 112 return read_cntvct(); 113 #else 114 return read_cntpct(); 115 #endif 116 } 117 #endif 118 119 #endif /*ARM_H*/ 120