1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rif.h> 9#include <dt-bindings/firewall/stm32mp25-rifsc.h> 10#include <dt-bindings/firewall/stm32mp25-risaf.h> 11#include <dt-bindings/firewall/stm32mp25-risab.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/st,stm32mp25-rcc.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a35"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0"; 33 method = "smc"; 34 }; 35 36 intc: interrupt-controller@4ac00000 { 37 compatible = "arm,cortex-a7-gic"; 38 #interrupt-cells = <3>; 39 interrupt-controller; 40 reg = <0x0 0x4ac10000 0x0 0x1000>, 41 <0x0 0x4ac20000 0x0 0x2000>, 42 <0x0 0x4ac40000 0x0 0x2000>, 43 <0x0 0x4ac60000 0x0 0x2000>; 44 #address-cells = <1>; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_msi: clk-msi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <0>; 82 }; 83 84 clk_rcbsec: clk-rcbsec { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 }; 90 91 soc@0 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&intc>; 96 ranges = <0x0 0x0 0x0 0x80000000>; 97 98 hpdma1: dma-controller@40400000 { 99 compatible = "st,stm32-dma3"; 100 reg = <0x40400000 0x1000>; 101 clocks = <&rcc CK_BUS_HPDMA1>; 102 resets = <&rcc HPDMA1_R>; 103 #dma-cells = <4>; 104 status = "disabled"; 105 }; 106 107 hpdma2: dma-controller@40410000 { 108 compatible = "st,stm32-dma3"; 109 reg = <0x40410000 0x1000>; 110 clocks = <&rcc CK_BUS_HPDMA2>; 111 resets = <&rcc HPDMA2_R>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 hpdma3: dma-controller@40420000 { 117 compatible = "st,stm32-dma3"; 118 reg = <0x40420000 0x1000>; 119 clocks = <&rcc CK_BUS_HPDMA3>; 120 resets = <&rcc HPDMA3_R>; 121 #dma-cells = <4>; 122 status = "disabled"; 123 }; 124 125 ipcc1: mailbox@40490000 { 126 compatible = "st,stm32mp25-ipcc"; 127 reg = <0x40490000 0x400>; 128 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "rx"; 130 clocks = <&rcc CK_BUS_IPCC1>; 131 status = "disabled"; 132 }; 133 134 ommanager: ommanager@40500000 { 135 compatible = "st,stm32mp25-omm"; 136 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 137 reg-names = "regs", "memory_map"; 138 ranges = <0 0 0x40430000 0x400>, 139 <1 0 0x40440000 0x400>; 140 clocks = <&rcc CK_BUS_OSPIIOM>; 141 resets = <&rcc OSPIIOM_R>; 142 #address-cells = <2>; 143 #size-cells = <1>; 144 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 145 status = "disabled"; 146 147 ospi1: spi@0 { 148 compatible = "st,stm32mp25-ospi"; 149 reg = <0 0 0x400>; 150 clocks = <&rcc CK_KER_OSPI1>; 151 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>; 152 status = "disabled"; 153 }; 154 155 ospi2: spi@1 { 156 compatible = "st,stm32mp25-ospi"; 157 reg = <1 0 0x400>; 158 clocks = <&rcc CK_KER_OSPI2>; 159 resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>; 160 status = "disabled"; 161 }; 162 }; 163 164 rifsc: rifsc@42080000 { 165 compatible = "st,stm32mp25-rifsc", "simple-bus"; 166 reg = <0x42080000 0x1000>; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 #access-controller-cells = <1>; 170 171 usart2: serial@400e0000 { 172 compatible = "st,stm32h7-uart"; 173 reg = <0x400e0000 0x400>; 174 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&rcc CK_KER_USART2>; 176 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 177 status = "disabled"; 178 }; 179 180 rng: rng@42020000 { 181 compatible = "st,stm32mp25-rng"; 182 reg = <0x42020000 0x400>; 183 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 184 clock-names = "rng_clk", "rng_hclk"; 185 resets = <&rcc RNG_R>; 186 access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>; 187 }; 188 }; 189 190 iac: iac@42090000 { 191 compatible = "st,stm32mp25-iac"; 192 reg = <0x42090000 0x400>; 193 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 194 }; 195 196 risaf1: risaf@420a0000 { 197 compatible = "st,stm32mp25-risaf"; 198 reg = <0x420a0000 0x1000>; 199 clocks = <&rcc CK_BUS_BKPSRAM>; 200 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 201 #access-controller-cells = <1>; 202 }; 203 204 risaf2: risaf@420b0000 { 205 compatible = "st,stm32mp25-risaf"; 206 reg = <0x420b0000 0x1000>; 207 clocks = <&rcc CK_KER_OSPI1>; 208 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 209 #access-controller-cells = <1>; 210 status = "disabled"; 211 }; 212 213 risaf4: risaf@420d0000 { 214 compatible = "st,stm32mp25-risaf-enc"; 215 reg = <0x420d0000 0x1000>; 216 clocks = <&rcc CK_BUS_RISAF4>; 217 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 218 #access-controller-cells = <1>; 219 }; 220 221 risaf5: risaf@420e0000 { 222 compatible = "st,stm32mp25-risaf"; 223 reg = <0x420e0000 0x1000>; 224 clocks = <&rcc CK_BUS_PCIE>; 225 st,mem-map = <0x0 0x10000000 0x0 0x10000000>; 226 #access-controller-cells = <1>; 227 status = "disabled"; 228 }; 229 230 risab1: risab@420f0000 { 231 compatible = "st,stm32mp25-risab"; 232 reg = <0x420f0000 0x1000>; 233 clocks = <&rcc CK_ICN_LS_MCU>; 234 st,mem-map = <0xa000000 0x20000>; 235 #access-controller-cells = <1>; 236 }; 237 238 risab2: risab@42100000 { 239 compatible = "st,stm32mp25-risab"; 240 reg = <0x42100000 0x1000>; 241 clocks = <&rcc CK_ICN_LS_MCU>; 242 st,mem-map = <0xa020000 0x20000>; 243 #access-controller-cells = <1>; 244 }; 245 246 risab3: risab@42110000 { 247 compatible = "st,stm32mp25-risab"; 248 reg = <0x42110000 0x1000>; 249 clocks = <&rcc CK_ICN_LS_MCU>; 250 st,mem-map = <0xa040000 0x20000>; 251 #access-controller-cells = <1>; 252 }; 253 254 risab4: risab@42120000 { 255 compatible = "st,stm32mp25-risab"; 256 reg = <0x42120000 0x1000>; 257 clocks = <&rcc CK_ICN_LS_MCU>; 258 st,mem-map = <0xa060000 0x20000>; 259 #access-controller-cells = <1>; 260 }; 261 262 risab5: risab@42130000 { 263 compatible = "st,stm32mp25-risab"; 264 reg = <0x42130000 0x1000>; 265 clocks = <&rcc CK_ICN_LS_MCU>; 266 st,mem-map = <0xa080000 0x20000>; 267 #access-controller-cells = <1>; 268 }; 269 270 risab6: risab@42140000 { 271 compatible = "st,stm32mp25-risab"; 272 reg = <0x42140000 0x1000>; 273 clocks = <&rcc CK_ICN_LS_MCU>; 274 st,mem-map = <0xa0a0000 0x20000>; 275 #access-controller-cells = <1>; 276 status = "disabled"; 277 }; 278 279 serc: serc@44080000 { 280 compatible = "st,stm32mp25-serc"; 281 reg = <0x44080000 0x1000>; 282 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&rcc CK_BUS_SERC>; 284 }; 285 286 rcc: rcc@44200000 { 287 compatible = "st,stm32mp25-rcc", "syscon"; 288 reg = <0x44200000 0x10000>; 289 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 290 291 #clock-cells = <1>; 292 #reset-cells = <1>; 293 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 294 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 295 clock-names = "clk-hse", "clk-hsi", "clk-lse", 296 "clk-lsi", "clk-msi", "clk-i2sin"; 297 298 hsi_calibration: hsi-calibration { 299 compatible = "st,hsi-cal"; 300 st,cal_hsi_dev = <31>; 301 st,cal_hsi_ref = <1953>; 302 status = "disabled"; 303 }; 304 305 msi_calibration: msi-calibration { 306 compatible = "st,msi-cal"; 307 status = "disabled"; 308 }; 309 }; 310 311 syscfg: syscon@44230000 { 312 reg = <0x44230000 0x10000>; 313 status = "disabled"; 314 }; 315 316 pinctrl: pinctrl@44240000 { 317 #address-cells = <1>; 318 #size-cells = <1>; 319 compatible = "st,stm32mp257-pinctrl"; 320 ranges = <0 0x44240000 0xa0400>; 321 pins-are-numbered; 322 323 gpioa: gpio@44240000 { 324 gpio-controller; 325 #gpio-cells = <2>; 326 interrupt-controller; 327 #interrupt-cells = <2>; 328 #access-controller-cells = <1>; 329 reg = <0x0 0x400>; 330 clocks = <&rcc CK_BUS_GPIOA>; 331 st,bank-name = "GPIOA"; 332 status = "disabled"; 333 }; 334 335 gpiob: gpio@44250000 { 336 gpio-controller; 337 #gpio-cells = <2>; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 #access-controller-cells = <1>; 341 reg = <0x10000 0x400>; 342 clocks = <&rcc CK_BUS_GPIOB>; 343 st,bank-name = "GPIOB"; 344 status = "disabled"; 345 }; 346 347 gpioc: gpio@44260000 { 348 gpio-controller; 349 #gpio-cells = <2>; 350 interrupt-controller; 351 #interrupt-cells = <2>; 352 #access-controller-cells = <1>; 353 reg = <0x20000 0x400>; 354 clocks = <&rcc CK_BUS_GPIOC>; 355 st,bank-name = "GPIOC"; 356 status = "disabled"; 357 }; 358 359 gpiod: gpio@44270000 { 360 gpio-controller; 361 #gpio-cells = <2>; 362 interrupt-controller; 363 #interrupt-cells = <2>; 364 #access-controller-cells = <1>; 365 reg = <0x30000 0x400>; 366 clocks = <&rcc CK_BUS_GPIOD>; 367 st,bank-name = "GPIOD"; 368 status = "disabled"; 369 }; 370 371 gpioe: gpio@44280000 { 372 gpio-controller; 373 #gpio-cells = <2>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 #access-controller-cells = <1>; 377 reg = <0x40000 0x400>; 378 clocks = <&rcc CK_BUS_GPIOE>; 379 st,bank-name = "GPIOE"; 380 status = "disabled"; 381 }; 382 383 gpiof: gpio@44290000 { 384 gpio-controller; 385 #gpio-cells = <2>; 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 #access-controller-cells = <1>; 389 reg = <0x50000 0x400>; 390 clocks = <&rcc CK_BUS_GPIOF>; 391 st,bank-name = "GPIOF"; 392 status = "disabled"; 393 }; 394 395 gpiog: gpio@442a0000 { 396 gpio-controller; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 #access-controller-cells = <1>; 401 reg = <0x60000 0x400>; 402 clocks = <&rcc CK_BUS_GPIOG>; 403 st,bank-name = "GPIOG"; 404 status = "disabled"; 405 }; 406 407 gpioh: gpio@442b0000 { 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 #access-controller-cells = <1>; 413 reg = <0x70000 0x400>; 414 clocks = <&rcc CK_BUS_GPIOH>; 415 st,bank-name = "GPIOH"; 416 status = "disabled"; 417 }; 418 419 gpioi: gpio@442c0000 { 420 gpio-controller; 421 #gpio-cells = <2>; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 #access-controller-cells = <1>; 425 reg = <0x80000 0x400>; 426 clocks = <&rcc CK_BUS_GPIOI>; 427 st,bank-name = "GPIOI"; 428 status = "disabled"; 429 }; 430 431 gpioj: gpio@442d0000 { 432 gpio-controller; 433 #gpio-cells = <2>; 434 interrupt-controller; 435 #interrupt-cells = <2>; 436 #access-controller-cells = <1>; 437 reg = <0x90000 0x400>; 438 clocks = <&rcc CK_BUS_GPIOJ>; 439 st,bank-name = "GPIOJ"; 440 status = "disabled"; 441 }; 442 443 gpiok: gpio@442e0000 { 444 gpio-controller; 445 #gpio-cells = <2>; 446 interrupt-controller; 447 #interrupt-cells = <2>; 448 #access-controller-cells = <1>; 449 reg = <0xa0000 0x400>; 450 clocks = <&rcc CK_BUS_GPIOK>; 451 st,bank-name = "GPIOK"; 452 status = "disabled"; 453 }; 454 }; 455 456 rtc: rtc@46000000 { 457 compatible = "st,stm32mp25-rtc"; 458 reg = <0x46000000 0x400>; 459 clocks = <&rcc CK_BUS_RTC>, <&rcc RTC_CK>; 460 clock-names = "pclk", "rtc_ck"; 461 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 462 }; 463 464 tamp: tamp@46010000 { 465 compatible = "st,stm32mp25-tamp"; 466 reg = <0x46010000 0x400>; 467 clocks = <&rcc CK_BUS_RTC>; 468 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 469 #address-cells = <1>; 470 #size-cells = <1>; 471 ranges; 472 st,backup-zones = <24 24 24 24 12 12 8>; 473 }; 474 475 pinctrl_z: pinctrl-z@46200000 { 476 #address-cells = <1>; 477 #size-cells = <1>; 478 compatible = "st,stm32mp257-z-pinctrl"; 479 ranges = <0 0x46200000 0x400>; 480 pins-are-numbered; 481 482 gpioz: gpio@46200000 { 483 gpio-controller; 484 #gpio-cells = <2>; 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 #access-controller-cells = <1>; 488 reg = <0 0x400>; 489 clocks = <&rcc CK_BUS_GPIOZ>; 490 st,bank-name = "GPIOZ"; 491 st,bank-ioport = <11>; 492 status = "disabled"; 493 }; 494 }; 495 496 hsem: hwspinlock@46240000 { 497 compatible = "st,stm32mp25-hsem"; 498 reg = <0x46240000 0x400>; 499 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&rcc CK_BUS_HSEM>; 501 status = "disabled"; 502 }; 503 504 ipcc2: mailbox@46250000 { 505 compatible = "st,stm32mp25-ipcc"; 506 reg = <0x46250000 0x400>; 507 clocks = <&rcc CK_BUS_IPCC2>; 508 status = "disabled"; 509 }; 510 511 stgenc: stgen@48080000 { 512 compatible = "st,stm32mp25-stgen"; 513 reg = <0x48080000 0x1000>; 514 clocks = <&rcc CK_BUS_STGEN>, <&rcc CK_KER_STGEN>; 515 clock-names = "bus", "stgen_clk"; 516 }; 517 518 fmc: memory-controller@48200000 { 519 #address-cells = <2>; 520 #size-cells = <1>; 521 compatible = "st,stm32mp25-fmc2-ebi"; 522 reg = <0x48200000 0x400>; 523 clocks = <&rcc CK_KER_FMC>; 524 resets = <&rcc FMC_R>; 525 status = "disabled"; 526 527 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 528 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 529 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 530 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 531 <4 0 0x80000000 0x10000000>; /* NAND */ 532 }; 533 }; 534}; 535