1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rif.h> 9#include <dt-bindings/firewall/stm32mp25-rifsc.h> 10#include <dt-bindings/firewall/stm32mp25-risaf.h> 11#include <dt-bindings/firewall/stm32mp25-risab.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/st,stm32mp25-rcc.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a35"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0"; 33 method = "smc"; 34 }; 35 36 intc: interrupt-controller@4ac00000 { 37 compatible = "arm,cortex-a7-gic"; 38 #interrupt-cells = <3>; 39 interrupt-controller; 40 reg = <0x0 0x4ac10000 0x0 0x1000>, 41 <0x0 0x4ac20000 0x0 0x2000>, 42 <0x0 0x4ac40000 0x0 0x2000>, 43 <0x0 0x4ac60000 0x0 0x2000>; 44 #address-cells = <1>; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_msi: clk-msi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <0>; 82 }; 83 84 clk_rcbsec: clk-rcbsec { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 }; 90 91 soc@0 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&intc>; 96 ranges = <0x0 0x0 0x0 0x80000000>; 97 98 hpdma1: dma-controller@40400000 { 99 compatible = "st,stm32-dma3"; 100 reg = <0x40400000 0x1000>; 101 clocks = <&rcc CK_BUS_HPDMA1>; 102 resets = <&rcc HPDMA1_R>; 103 #dma-cells = <4>; 104 status = "disabled"; 105 }; 106 107 hpdma2: dma-controller@40410000 { 108 compatible = "st,stm32-dma3"; 109 reg = <0x40410000 0x1000>; 110 clocks = <&rcc CK_BUS_HPDMA2>; 111 resets = <&rcc HPDMA2_R>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 hpdma3: dma-controller@40420000 { 117 compatible = "st,stm32-dma3"; 118 reg = <0x40420000 0x1000>; 119 clocks = <&rcc CK_BUS_HPDMA3>; 120 resets = <&rcc HPDMA3_R>; 121 #dma-cells = <4>; 122 status = "disabled"; 123 }; 124 125 ipcc1: mailbox@40490000 { 126 compatible = "st,stm32mp25-ipcc"; 127 reg = <0x40490000 0x400>; 128 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "rx"; 130 clocks = <&rcc CK_BUS_IPCC1>; 131 status = "disabled"; 132 }; 133 134 rifsc: rifsc@42080000 { 135 compatible = "st,stm32mp25-rifsc", "simple-bus"; 136 reg = <0x42080000 0x1000>; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 #access-controller-cells = <1>; 140 141 usart2: serial@400e0000 { 142 compatible = "st,stm32h7-uart"; 143 reg = <0x400e0000 0x400>; 144 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&rcc CK_KER_USART2>; 146 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 147 status = "disabled"; 148 }; 149 150 rng: rng@42020000 { 151 compatible = "st,stm32mp25-rng"; 152 reg = <0x42020000 0x400>; 153 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 154 clock-names = "rng_clk", "rng_hclk"; 155 resets = <&rcc RNG_R>; 156 access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>; 157 }; 158 }; 159 160 iac: iac@42090000 { 161 compatible = "st,stm32mp25-iac"; 162 reg = <0x42090000 0x400>; 163 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 164 }; 165 166 risaf1: risaf@420a0000 { 167 compatible = "st,stm32mp25-risaf"; 168 reg = <0x420a0000 0x1000>; 169 clocks = <&rcc CK_BUS_BKPSRAM>; 170 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 171 #access-controller-cells = <1>; 172 }; 173 174 risaf2: risaf@420b0000 { 175 compatible = "st,stm32mp25-risaf"; 176 reg = <0x420b0000 0x1000>; 177 clocks = <&rcc CK_KER_OSPI1>; 178 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 179 #access-controller-cells = <1>; 180 status = "disabled"; 181 }; 182 183 risaf4: risaf@420d0000 { 184 compatible = "st,stm32mp25-risaf-enc"; 185 reg = <0x420d0000 0x1000>; 186 clocks = <&rcc CK_BUS_RISAF4>; 187 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 188 #access-controller-cells = <1>; 189 }; 190 191 risaf5: risaf@420e0000 { 192 compatible = "st,stm32mp25-risaf"; 193 reg = <0x420e0000 0x1000>; 194 clocks = <&rcc CK_BUS_PCIE>; 195 st,mem-map = <0x0 0x10000000 0x0 0x10000000>; 196 #access-controller-cells = <1>; 197 status = "disabled"; 198 }; 199 200 risab1: risab@420f0000 { 201 compatible = "st,stm32mp25-risab"; 202 reg = <0x420f0000 0x1000>; 203 clocks = <&rcc CK_ICN_LS_MCU>; 204 st,mem-map = <0xa000000 0x20000>; 205 #access-controller-cells = <1>; 206 }; 207 208 risab2: risab@42100000 { 209 compatible = "st,stm32mp25-risab"; 210 reg = <0x42100000 0x1000>; 211 clocks = <&rcc CK_ICN_LS_MCU>; 212 st,mem-map = <0xa020000 0x20000>; 213 #access-controller-cells = <1>; 214 }; 215 216 risab3: risab@42110000 { 217 compatible = "st,stm32mp25-risab"; 218 reg = <0x42110000 0x1000>; 219 clocks = <&rcc CK_ICN_LS_MCU>; 220 st,mem-map = <0xa040000 0x20000>; 221 #access-controller-cells = <1>; 222 }; 223 224 risab4: risab@42120000 { 225 compatible = "st,stm32mp25-risab"; 226 reg = <0x42120000 0x1000>; 227 clocks = <&rcc CK_ICN_LS_MCU>; 228 st,mem-map = <0xa060000 0x20000>; 229 #access-controller-cells = <1>; 230 }; 231 232 risab5: risab@42130000 { 233 compatible = "st,stm32mp25-risab"; 234 reg = <0x42130000 0x1000>; 235 clocks = <&rcc CK_ICN_LS_MCU>; 236 st,mem-map = <0xa080000 0x20000>; 237 #access-controller-cells = <1>; 238 }; 239 240 risab6: risab@42140000 { 241 compatible = "st,stm32mp25-risab"; 242 reg = <0x42140000 0x1000>; 243 clocks = <&rcc CK_ICN_LS_MCU>; 244 st,mem-map = <0xa0a0000 0x20000>; 245 #access-controller-cells = <1>; 246 status = "disabled"; 247 }; 248 249 serc: serc@44080000 { 250 compatible = "st,stm32mp25-serc"; 251 reg = <0x44080000 0x1000>; 252 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&rcc CK_BUS_SERC>; 254 }; 255 256 rcc: rcc@44200000 { 257 compatible = "st,stm32mp25-rcc", "syscon"; 258 reg = <0x44200000 0x10000>; 259 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 260 261 #clock-cells = <1>; 262 #reset-cells = <1>; 263 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 264 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 265 clock-names = "clk-hse", "clk-hsi", "clk-lse", 266 "clk-lsi", "clk-msi", "clk-i2sin"; 267 268 hsi_calibration: hsi-calibration { 269 compatible = "st,hsi-cal"; 270 st,cal_hsi_dev = <31>; 271 st,cal_hsi_ref = <1953>; 272 status = "disabled"; 273 }; 274 275 msi_calibration: msi-calibration { 276 compatible = "st,msi-cal"; 277 status = "disabled"; 278 }; 279 }; 280 281 pinctrl: pinctrl@44240000 { 282 #address-cells = <1>; 283 #size-cells = <1>; 284 compatible = "st,stm32mp257-pinctrl"; 285 ranges = <0 0x44240000 0xa0400>; 286 pins-are-numbered; 287 288 gpioa: gpio@44240000 { 289 gpio-controller; 290 #gpio-cells = <2>; 291 interrupt-controller; 292 #interrupt-cells = <2>; 293 #access-controller-cells = <1>; 294 reg = <0x0 0x400>; 295 clocks = <&rcc CK_BUS_GPIOA>; 296 st,bank-name = "GPIOA"; 297 status = "disabled"; 298 }; 299 300 gpiob: gpio@44250000 { 301 gpio-controller; 302 #gpio-cells = <2>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 #access-controller-cells = <1>; 306 reg = <0x10000 0x400>; 307 clocks = <&rcc CK_BUS_GPIOB>; 308 st,bank-name = "GPIOB"; 309 status = "disabled"; 310 }; 311 312 gpioc: gpio@44260000 { 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 #access-controller-cells = <1>; 318 reg = <0x20000 0x400>; 319 clocks = <&rcc CK_BUS_GPIOC>; 320 st,bank-name = "GPIOC"; 321 status = "disabled"; 322 }; 323 324 gpiod: gpio@44270000 { 325 gpio-controller; 326 #gpio-cells = <2>; 327 interrupt-controller; 328 #interrupt-cells = <2>; 329 #access-controller-cells = <1>; 330 reg = <0x30000 0x400>; 331 clocks = <&rcc CK_BUS_GPIOD>; 332 st,bank-name = "GPIOD"; 333 status = "disabled"; 334 }; 335 336 gpioe: gpio@44280000 { 337 gpio-controller; 338 #gpio-cells = <2>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 #access-controller-cells = <1>; 342 reg = <0x40000 0x400>; 343 clocks = <&rcc CK_BUS_GPIOE>; 344 st,bank-name = "GPIOE"; 345 status = "disabled"; 346 }; 347 348 gpiof: gpio@44290000 { 349 gpio-controller; 350 #gpio-cells = <2>; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 #access-controller-cells = <1>; 354 reg = <0x50000 0x400>; 355 clocks = <&rcc CK_BUS_GPIOF>; 356 st,bank-name = "GPIOF"; 357 status = "disabled"; 358 }; 359 360 gpiog: gpio@442a0000 { 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 #access-controller-cells = <1>; 366 reg = <0x60000 0x400>; 367 clocks = <&rcc CK_BUS_GPIOG>; 368 st,bank-name = "GPIOG"; 369 status = "disabled"; 370 }; 371 372 gpioh: gpio@442b0000 { 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 #access-controller-cells = <1>; 378 reg = <0x70000 0x400>; 379 clocks = <&rcc CK_BUS_GPIOH>; 380 st,bank-name = "GPIOH"; 381 status = "disabled"; 382 }; 383 384 gpioi: gpio@442c0000 { 385 gpio-controller; 386 #gpio-cells = <2>; 387 interrupt-controller; 388 #interrupt-cells = <2>; 389 #access-controller-cells = <1>; 390 reg = <0x80000 0x400>; 391 clocks = <&rcc CK_BUS_GPIOI>; 392 st,bank-name = "GPIOI"; 393 status = "disabled"; 394 }; 395 396 gpioj: gpio@442d0000 { 397 gpio-controller; 398 #gpio-cells = <2>; 399 interrupt-controller; 400 #interrupt-cells = <2>; 401 #access-controller-cells = <1>; 402 reg = <0x90000 0x400>; 403 clocks = <&rcc CK_BUS_GPIOJ>; 404 st,bank-name = "GPIOJ"; 405 status = "disabled"; 406 }; 407 408 gpiok: gpio@442e0000 { 409 gpio-controller; 410 #gpio-cells = <2>; 411 interrupt-controller; 412 #interrupt-cells = <2>; 413 #access-controller-cells = <1>; 414 reg = <0xa0000 0x400>; 415 clocks = <&rcc CK_BUS_GPIOK>; 416 st,bank-name = "GPIOK"; 417 status = "disabled"; 418 }; 419 }; 420 421 rtc: rtc@46000000 { 422 compatible = "st,stm32mp25-rtc"; 423 reg = <0x46000000 0x400>; 424 clocks = <&rcc CK_BUS_RTC>, <&rcc RTC_CK>; 425 clock-names = "pclk", "rtc_ck"; 426 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 427 }; 428 429 tamp: tamp@46010000 { 430 compatible = "st,stm32mp25-tamp"; 431 reg = <0x46010000 0x400>; 432 clocks = <&rcc CK_BUS_RTC>; 433 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 434 #address-cells = <1>; 435 #size-cells = <1>; 436 ranges; 437 st,backup-zones = <24 24 24 24 12 12 8>; 438 }; 439 440 pinctrl_z: pinctrl-z@46200000 { 441 #address-cells = <1>; 442 #size-cells = <1>; 443 compatible = "st,stm32mp257-z-pinctrl"; 444 ranges = <0 0x46200000 0x400>; 445 pins-are-numbered; 446 447 gpioz: gpio@46200000 { 448 gpio-controller; 449 #gpio-cells = <2>; 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 #access-controller-cells = <1>; 453 reg = <0 0x400>; 454 clocks = <&rcc CK_BUS_GPIOZ>; 455 st,bank-name = "GPIOZ"; 456 st,bank-ioport = <11>; 457 status = "disabled"; 458 }; 459 }; 460 461 hsem: hwspinlock@46240000 { 462 compatible = "st,stm32mp25-hsem"; 463 reg = <0x46240000 0x400>; 464 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&rcc CK_BUS_HSEM>; 466 status = "disabled"; 467 }; 468 469 ipcc2: mailbox@46250000 { 470 compatible = "st,stm32mp25-ipcc"; 471 reg = <0x46250000 0x400>; 472 clocks = <&rcc CK_BUS_IPCC2>; 473 status = "disabled"; 474 }; 475 476 stgenc: stgen@48080000 { 477 compatible = "st,stm32mp25-stgen"; 478 reg = <0x48080000 0x1000>; 479 clocks = <&rcc CK_BUS_STGEN>, <&rcc CK_KER_STGEN>; 480 clock-names = "bus", "stgen_clk"; 481 }; 482 483 fmc: memory-controller@48200000 { 484 #address-cells = <2>; 485 #size-cells = <1>; 486 compatible = "st,stm32mp25-fmc2-ebi"; 487 reg = <0x48200000 0x400>; 488 clocks = <&rcc CK_KER_FMC>; 489 resets = <&rcc FMC_R>; 490 status = "disabled"; 491 492 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 493 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 494 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 495 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 496 <4 0 0x80000000 0x10000000>; /* NAND */ 497 }; 498 }; 499}; 500