1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/st,stm32mp25-rcc.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 }; 25 }; 26 27 psci { 28 compatible = "arm,psci-1.0"; 29 method = "smc"; 30 }; 31 32 intc: interrupt-controller@4ac00000 { 33 compatible = "arm,cortex-a7-gic"; 34 #interrupt-cells = <3>; 35 interrupt-controller; 36 reg = <0x0 0x4ac10000 0x0 0x1000>, 37 <0x0 0x4ac20000 0x0 0x2000>, 38 <0x0 0x4ac40000 0x0 0x2000>, 39 <0x0 0x4ac60000 0x0 0x2000>; 40 #address-cells = <1>; 41 }; 42 43 clocks { 44 clk_hse: clk-hse { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <24000000>; 48 }; 49 50 clk_hsi: clk-hsi { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <64000000>; 54 }; 55 56 clk_lse: clk-lse { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <32768>; 60 }; 61 62 clk_lsi: clk-lsi { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <32000>; 66 }; 67 68 clk_msi: clk-msi { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 clock-frequency = <4000000>; 72 }; 73 74 clk_i2sin: clk-i2sin { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <0>; 78 }; 79 80 clk_rcbsec: clk-rcbsec { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <64000000>; 84 }; 85 }; 86 87 soc@0 { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 interrupt-parent = <&intc>; 92 ranges = <0x0 0x0 0x0 0x80000000>; 93 94 hpdma1: dma-controller@40400000 { 95 compatible = "st,stm32-dma3"; 96 reg = <0x40400000 0x1000>; 97 #dma-cells = <4>; 98 status = "disabled"; 99 }; 100 101 hpdma2: dma-controller@40410000 { 102 compatible = "st,stm32-dma3"; 103 reg = <0x40410000 0x1000>; 104 #dma-cells = <4>; 105 status = "disabled"; 106 }; 107 108 hpdma3: dma-controller@40420000 { 109 compatible = "st,stm32-dma3"; 110 reg = <0x40420000 0x1000>; 111 #dma-cells = <4>; 112 status = "disabled"; 113 }; 114 115 ipcc1: mailbox@40490000 { 116 compatible = "st,stm32mp25-ipcc"; 117 reg = <0x40490000 0x400>; 118 status = "disabled"; 119 }; 120 121 rifsc: rifsc@42080000 { 122 compatible = "st,stm32mp25-rifsc"; 123 reg = <0x42080000 0x1000>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 127 usart2: serial@400e0000 { 128 reg = <0x400e0000 0x400>; 129 status = "disabled"; 130 }; 131 }; 132 133 rcc: rcc@44200000 { 134 compatible = "st,stm32mp25-rcc", "syscon"; 135 reg = <0x44200000 0x10000>; 136 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 137 138 #clock-cells = <1>; 139 #reset-cells = <1>; 140 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 141 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 142 clock-names = "clk-hse", "clk-hsi", "clk-lse", 143 "clk-lsi", "clk-msi", "clk-i2sin"; 144 145 hsi_calibration: hsi-calibration { 146 compatible = "st,hsi-cal"; 147 st,cal_hsi_dev = <31>; 148 st,cal_hsi_ref = <1953>; 149 status = "disabled"; 150 }; 151 152 msi_calibration: msi-calibration { 153 compatible = "st,msi-cal"; 154 status = "disabled"; 155 }; 156 }; 157 158 pinctrl: pinctrl@44240000 { 159 #address-cells = <1>; 160 #size-cells = <1>; 161 compatible = "st,stm32mp257-pinctrl"; 162 ranges = <0 0x44240000 0xa0400>; 163 pins-are-numbered; 164 165 gpioa: gpio@44240000 { 166 gpio-controller; 167 #gpio-cells = <2>; 168 interrupt-controller; 169 #interrupt-cells = <2>; 170 reg = <0x0 0x400>; 171 clocks = <&rcc CK_BUS_GPIOA>; 172 st,bank-name = "GPIOA"; 173 status = "disabled"; 174 }; 175 176 gpiob: gpio@44250000 { 177 gpio-controller; 178 #gpio-cells = <2>; 179 interrupt-controller; 180 #interrupt-cells = <2>; 181 reg = <0x10000 0x400>; 182 clocks = <&rcc CK_BUS_GPIOB>; 183 st,bank-name = "GPIOB"; 184 status = "disabled"; 185 }; 186 187 gpioc: gpio@44260000 { 188 gpio-controller; 189 #gpio-cells = <2>; 190 interrupt-controller; 191 #interrupt-cells = <2>; 192 reg = <0x20000 0x400>; 193 clocks = <&rcc CK_BUS_GPIOC>; 194 st,bank-name = "GPIOC"; 195 status = "disabled"; 196 }; 197 198 gpiod: gpio@44270000 { 199 gpio-controller; 200 #gpio-cells = <2>; 201 interrupt-controller; 202 #interrupt-cells = <2>; 203 reg = <0x30000 0x400>; 204 clocks = <&rcc CK_BUS_GPIOD>; 205 st,bank-name = "GPIOD"; 206 status = "disabled"; 207 }; 208 209 gpioe: gpio@44280000 { 210 gpio-controller; 211 #gpio-cells = <2>; 212 interrupt-controller; 213 #interrupt-cells = <2>; 214 reg = <0x40000 0x400>; 215 clocks = <&rcc CK_BUS_GPIOE>; 216 st,bank-name = "GPIOE"; 217 status = "disabled"; 218 }; 219 220 gpiof: gpio@44290000 { 221 gpio-controller; 222 #gpio-cells = <2>; 223 interrupt-controller; 224 #interrupt-cells = <2>; 225 reg = <0x50000 0x400>; 226 clocks = <&rcc CK_BUS_GPIOF>; 227 st,bank-name = "GPIOF"; 228 status = "disabled"; 229 }; 230 231 gpiog: gpio@442a0000 { 232 gpio-controller; 233 #gpio-cells = <2>; 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 reg = <0x60000 0x400>; 237 clocks = <&rcc CK_BUS_GPIOG>; 238 st,bank-name = "GPIOG"; 239 status = "disabled"; 240 }; 241 242 gpioh: gpio@442b0000 { 243 gpio-controller; 244 #gpio-cells = <2>; 245 interrupt-controller; 246 #interrupt-cells = <2>; 247 reg = <0x70000 0x400>; 248 clocks = <&rcc CK_BUS_GPIOH>; 249 st,bank-name = "GPIOH"; 250 status = "disabled"; 251 }; 252 253 gpioi: gpio@442c0000 { 254 gpio-controller; 255 #gpio-cells = <2>; 256 interrupt-controller; 257 #interrupt-cells = <2>; 258 reg = <0x80000 0x400>; 259 clocks = <&rcc CK_BUS_GPIOI>; 260 st,bank-name = "GPIOI"; 261 status = "disabled"; 262 }; 263 264 gpioj: gpio@442d0000 { 265 gpio-controller; 266 #gpio-cells = <2>; 267 interrupt-controller; 268 #interrupt-cells = <2>; 269 reg = <0x90000 0x400>; 270 clocks = <&rcc CK_BUS_GPIOJ>; 271 st,bank-name = "GPIOJ"; 272 status = "disabled"; 273 }; 274 275 gpiok: gpio@442e0000 { 276 gpio-controller; 277 #gpio-cells = <2>; 278 interrupt-controller; 279 #interrupt-cells = <2>; 280 reg = <0xa0000 0x400>; 281 clocks = <&rcc CK_BUS_GPIOK>; 282 st,bank-name = "GPIOK"; 283 status = "disabled"; 284 }; 285 }; 286 287 pinctrl_z: pinctrl-z@46200000 { 288 #address-cells = <1>; 289 #size-cells = <1>; 290 compatible = "st,stm32mp257-z-pinctrl"; 291 ranges = <0 0x46200000 0x400>; 292 pins-are-numbered; 293 294 gpioz: gpio@46200000 { 295 gpio-controller; 296 #gpio-cells = <2>; 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 reg = <0 0x400>; 300 clocks = <&rcc CK_BUS_GPIOZ>; 301 st,bank-name = "GPIOZ"; 302 st,bank-ioport = <11>; 303 status = "disabled"; 304 }; 305 }; 306 307 hsem: hwspinlock@46240000 { 308 compatible = "st,stm32mp25-hsem"; 309 reg = <0x46240000 0x400>; 310 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 311 status = "disabled"; 312 }; 313 314 ipcc2: mailbox@46250000 { 315 compatible = "st,stm32mp25-ipcc"; 316 reg = <0x46250000 0x400>; 317 status = "disabled"; 318 }; 319 320 fmc: memory-controller@48200000 { 321 #address-cells = <2>; 322 #size-cells = <1>; 323 compatible = "st,stm32mp25-fmc2-ebi"; 324 reg = <0x48200000 0x400>; 325 status = "disabled"; 326 327 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 328 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 329 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 330 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 331 <4 0 0x80000000 0x10000000>; /* NAND */ 332 }; 333 }; 334}; 335