1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rifsc.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/reset/st,stm32mp25-rcc.h> 11 12/ { 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a35"; 22 device_type = "cpu"; 23 reg = <0>; 24 enable-method = "psci"; 25 }; 26 }; 27 28 psci { 29 compatible = "arm,psci-1.0"; 30 method = "smc"; 31 }; 32 33 intc: interrupt-controller@4ac00000 { 34 compatible = "arm,cortex-a7-gic"; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x0 0x4ac10000 0x0 0x1000>, 38 <0x0 0x4ac20000 0x0 0x2000>, 39 <0x0 0x4ac40000 0x0 0x2000>, 40 <0x0 0x4ac60000 0x0 0x2000>; 41 #address-cells = <1>; 42 }; 43 44 clocks { 45 clk_hse: clk-hse { 46 #clock-cells = <0>; 47 compatible = "fixed-clock"; 48 clock-frequency = <24000000>; 49 }; 50 51 clk_hsi: clk-hsi { 52 #clock-cells = <0>; 53 compatible = "fixed-clock"; 54 clock-frequency = <64000000>; 55 }; 56 57 clk_lse: clk-lse { 58 #clock-cells = <0>; 59 compatible = "fixed-clock"; 60 clock-frequency = <32768>; 61 }; 62 63 clk_lsi: clk-lsi { 64 #clock-cells = <0>; 65 compatible = "fixed-clock"; 66 clock-frequency = <32000>; 67 }; 68 69 clk_msi: clk-msi { 70 #clock-cells = <0>; 71 compatible = "fixed-clock"; 72 clock-frequency = <4000000>; 73 }; 74 75 clk_i2sin: clk-i2sin { 76 #clock-cells = <0>; 77 compatible = "fixed-clock"; 78 clock-frequency = <0>; 79 }; 80 81 clk_rcbsec: clk-rcbsec { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <64000000>; 85 }; 86 }; 87 88 soc@0 { 89 compatible = "simple-bus"; 90 #address-cells = <1>; 91 #size-cells = <1>; 92 interrupt-parent = <&intc>; 93 ranges = <0x0 0x0 0x0 0x80000000>; 94 95 hpdma1: dma-controller@40400000 { 96 compatible = "st,stm32-dma3"; 97 reg = <0x40400000 0x1000>; 98 #dma-cells = <4>; 99 status = "disabled"; 100 }; 101 102 hpdma2: dma-controller@40410000 { 103 compatible = "st,stm32-dma3"; 104 reg = <0x40410000 0x1000>; 105 #dma-cells = <4>; 106 status = "disabled"; 107 }; 108 109 hpdma3: dma-controller@40420000 { 110 compatible = "st,stm32-dma3"; 111 reg = <0x40420000 0x1000>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 ipcc1: mailbox@40490000 { 117 compatible = "st,stm32mp25-ipcc"; 118 reg = <0x40490000 0x400>; 119 status = "disabled"; 120 }; 121 122 rifsc: rifsc@42080000 { 123 compatible = "st,stm32mp25-rifsc"; 124 reg = <0x42080000 0x1000>; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 128 usart2: serial@400e0000 { 129 compatible = "st,stm32h7-uart"; 130 reg = <0x400e0000 0x400>; 131 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&rcc CK_KER_USART2>; 133 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 134 status = "disabled"; 135 }; 136 }; 137 138 iac: iac@42090000 { 139 compatible = "st,stm32mp25-iac"; 140 reg = <0x42090000 0x400>; 141 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 142 }; 143 144 risaf1: risaf@420a0000 { 145 compatible = "st,stm32mp25-risaf"; 146 reg = <0x420a0000 0x1000>; 147 clocks = <&rcc CK_BUS_BKPSRAM>; 148 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 149 }; 150 151 risaf2: risaf@420b0000 { 152 compatible = "st,stm32mp25-risaf"; 153 reg = <0x420b0000 0x1000>; 154 clocks = <&rcc CK_KER_OSPI1>; 155 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 156 status = "disabled"; 157 }; 158 159 risaf4: risaf@420d0000 { 160 compatible = "st,stm32mp25-risaf-enc"; 161 reg = <0x420d0000 0x1000>; 162 clocks = <&rcc CK_BUS_RISAF4>; 163 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 164 }; 165 166 risaf5: risaf@420e0000 { 167 compatible = "st,stm32mp25-risaf"; 168 reg = <0x420e0000 0x1000>; 169 clocks = <&rcc CK_BUS_PCIE>; 170 st,mem-map = <0x0 0x10000000 0x0 0x10000000>; 171 status = "disabled"; 172 }; 173 174 serc: serc@44080000 { 175 compatible = "st,stm32mp25-serc"; 176 reg = <0x44080000 0x1000>; 177 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&rcc CK_BUS_SERC>; 179 }; 180 181 rcc: rcc@44200000 { 182 compatible = "st,stm32mp25-rcc", "syscon"; 183 reg = <0x44200000 0x10000>; 184 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 185 186 #clock-cells = <1>; 187 #reset-cells = <1>; 188 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 189 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 190 clock-names = "clk-hse", "clk-hsi", "clk-lse", 191 "clk-lsi", "clk-msi", "clk-i2sin"; 192 193 hsi_calibration: hsi-calibration { 194 compatible = "st,hsi-cal"; 195 st,cal_hsi_dev = <31>; 196 st,cal_hsi_ref = <1953>; 197 status = "disabled"; 198 }; 199 200 msi_calibration: msi-calibration { 201 compatible = "st,msi-cal"; 202 status = "disabled"; 203 }; 204 }; 205 206 pinctrl: pinctrl@44240000 { 207 #address-cells = <1>; 208 #size-cells = <1>; 209 compatible = "st,stm32mp257-pinctrl"; 210 ranges = <0 0x44240000 0xa0400>; 211 pins-are-numbered; 212 213 gpioa: gpio@44240000 { 214 gpio-controller; 215 #gpio-cells = <2>; 216 interrupt-controller; 217 #interrupt-cells = <2>; 218 reg = <0x0 0x400>; 219 clocks = <&rcc CK_BUS_GPIOA>; 220 st,bank-name = "GPIOA"; 221 status = "disabled"; 222 }; 223 224 gpiob: gpio@44250000 { 225 gpio-controller; 226 #gpio-cells = <2>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 reg = <0x10000 0x400>; 230 clocks = <&rcc CK_BUS_GPIOB>; 231 st,bank-name = "GPIOB"; 232 status = "disabled"; 233 }; 234 235 gpioc: gpio@44260000 { 236 gpio-controller; 237 #gpio-cells = <2>; 238 interrupt-controller; 239 #interrupt-cells = <2>; 240 reg = <0x20000 0x400>; 241 clocks = <&rcc CK_BUS_GPIOC>; 242 st,bank-name = "GPIOC"; 243 status = "disabled"; 244 }; 245 246 gpiod: gpio@44270000 { 247 gpio-controller; 248 #gpio-cells = <2>; 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 reg = <0x30000 0x400>; 252 clocks = <&rcc CK_BUS_GPIOD>; 253 st,bank-name = "GPIOD"; 254 status = "disabled"; 255 }; 256 257 gpioe: gpio@44280000 { 258 gpio-controller; 259 #gpio-cells = <2>; 260 interrupt-controller; 261 #interrupt-cells = <2>; 262 reg = <0x40000 0x400>; 263 clocks = <&rcc CK_BUS_GPIOE>; 264 st,bank-name = "GPIOE"; 265 status = "disabled"; 266 }; 267 268 gpiof: gpio@44290000 { 269 gpio-controller; 270 #gpio-cells = <2>; 271 interrupt-controller; 272 #interrupt-cells = <2>; 273 reg = <0x50000 0x400>; 274 clocks = <&rcc CK_BUS_GPIOF>; 275 st,bank-name = "GPIOF"; 276 status = "disabled"; 277 }; 278 279 gpiog: gpio@442a0000 { 280 gpio-controller; 281 #gpio-cells = <2>; 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 reg = <0x60000 0x400>; 285 clocks = <&rcc CK_BUS_GPIOG>; 286 st,bank-name = "GPIOG"; 287 status = "disabled"; 288 }; 289 290 gpioh: gpio@442b0000 { 291 gpio-controller; 292 #gpio-cells = <2>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 reg = <0x70000 0x400>; 296 clocks = <&rcc CK_BUS_GPIOH>; 297 st,bank-name = "GPIOH"; 298 status = "disabled"; 299 }; 300 301 gpioi: gpio@442c0000 { 302 gpio-controller; 303 #gpio-cells = <2>; 304 interrupt-controller; 305 #interrupt-cells = <2>; 306 reg = <0x80000 0x400>; 307 clocks = <&rcc CK_BUS_GPIOI>; 308 st,bank-name = "GPIOI"; 309 status = "disabled"; 310 }; 311 312 gpioj: gpio@442d0000 { 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 reg = <0x90000 0x400>; 318 clocks = <&rcc CK_BUS_GPIOJ>; 319 st,bank-name = "GPIOJ"; 320 status = "disabled"; 321 }; 322 323 gpiok: gpio@442e0000 { 324 gpio-controller; 325 #gpio-cells = <2>; 326 interrupt-controller; 327 #interrupt-cells = <2>; 328 reg = <0xa0000 0x400>; 329 clocks = <&rcc CK_BUS_GPIOK>; 330 st,bank-name = "GPIOK"; 331 status = "disabled"; 332 }; 333 }; 334 335 pinctrl_z: pinctrl-z@46200000 { 336 #address-cells = <1>; 337 #size-cells = <1>; 338 compatible = "st,stm32mp257-z-pinctrl"; 339 ranges = <0 0x46200000 0x400>; 340 pins-are-numbered; 341 342 gpioz: gpio@46200000 { 343 gpio-controller; 344 #gpio-cells = <2>; 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 reg = <0 0x400>; 348 clocks = <&rcc CK_BUS_GPIOZ>; 349 st,bank-name = "GPIOZ"; 350 st,bank-ioport = <11>; 351 status = "disabled"; 352 }; 353 }; 354 355 hsem: hwspinlock@46240000 { 356 compatible = "st,stm32mp25-hsem"; 357 reg = <0x46240000 0x400>; 358 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 359 status = "disabled"; 360 }; 361 362 ipcc2: mailbox@46250000 { 363 compatible = "st,stm32mp25-ipcc"; 364 reg = <0x46250000 0x400>; 365 status = "disabled"; 366 }; 367 368 fmc: memory-controller@48200000 { 369 #address-cells = <2>; 370 #size-cells = <1>; 371 compatible = "st,stm32mp25-fmc2-ebi"; 372 reg = <0x48200000 0x400>; 373 status = "disabled"; 374 375 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 376 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 377 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 378 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 379 <4 0 0x80000000 0x10000000>; /* NAND */ 380 }; 381 }; 382}; 383