1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/reset/st,stm32mp25-rcc.h> 10 11/ { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a35"; 21 device_type = "cpu"; 22 reg = <0>; 23 enable-method = "psci"; 24 }; 25 }; 26 27 psci { 28 compatible = "arm,psci-1.0"; 29 method = "smc"; 30 }; 31 32 intc: interrupt-controller@4ac00000 { 33 compatible = "arm,cortex-a7-gic"; 34 #interrupt-cells = <3>; 35 interrupt-controller; 36 reg = <0x0 0x4ac10000 0x0 0x1000>, 37 <0x0 0x4ac20000 0x0 0x2000>, 38 <0x0 0x4ac40000 0x0 0x2000>, 39 <0x0 0x4ac60000 0x0 0x2000>; 40 #address-cells = <1>; 41 }; 42 43 clocks { 44 clk_hse: clk-hse { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <24000000>; 48 }; 49 50 clk_hsi: clk-hsi { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <64000000>; 54 }; 55 56 clk_lse: clk-lse { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <32768>; 60 }; 61 62 clk_lsi: clk-lsi { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <32000>; 66 }; 67 68 clk_msi: clk-msi { 69 #clock-cells = <0>; 70 compatible = "fixed-clock"; 71 clock-frequency = <4000000>; 72 }; 73 74 clk_i2sin: clk-i2sin { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <0>; 78 }; 79 80 clk_rcbsec: clk-rcbsec { 81 #clock-cells = <0>; 82 compatible = "fixed-clock"; 83 clock-frequency = <64000000>; 84 }; 85 }; 86 87 soc@0 { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 interrupt-parent = <&intc>; 92 ranges = <0x0 0x0 0x0 0x80000000>; 93 94 hpdma1: dma-controller@40400000 { 95 compatible = "st,stm32-dma3"; 96 reg = <0x40400000 0x1000>; 97 #dma-cells = <4>; 98 status = "disabled"; 99 }; 100 101 hpdma2: dma-controller@40410000 { 102 compatible = "st,stm32-dma3"; 103 reg = <0x40410000 0x1000>; 104 #dma-cells = <4>; 105 status = "disabled"; 106 }; 107 108 hpdma3: dma-controller@40420000 { 109 compatible = "st,stm32-dma3"; 110 reg = <0x40420000 0x1000>; 111 #dma-cells = <4>; 112 status = "disabled"; 113 }; 114 115 ipcc1: mailbox@40490000 { 116 compatible = "st,stm32mp25-ipcc"; 117 reg = <0x40490000 0x400>; 118 status = "disabled"; 119 }; 120 121 rifsc: rifsc@42080000 { 122 compatible = "st,stm32mp25-rifsc"; 123 reg = <0x42080000 0x1000>; 124 #address-cells = <1>; 125 #size-cells = <1>; 126 127 usart2: serial@400e0000 { 128 reg = <0x400e0000 0x400>; 129 status = "disabled"; 130 }; 131 }; 132 133 iac: iac@42090000 { 134 compatible = "st,stm32mp25-iac"; 135 reg = <0x42090000 0x400>; 136 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 137 }; 138 139 serc: serc@44080000 { 140 compatible = "st,stm32mp25-serc"; 141 reg = <0x44080000 0x1000>; 142 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&rcc CK_BUS_SERC>; 144 }; 145 146 rcc: rcc@44200000 { 147 compatible = "st,stm32mp25-rcc", "syscon"; 148 reg = <0x44200000 0x10000>; 149 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 150 151 #clock-cells = <1>; 152 #reset-cells = <1>; 153 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 154 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 155 clock-names = "clk-hse", "clk-hsi", "clk-lse", 156 "clk-lsi", "clk-msi", "clk-i2sin"; 157 158 hsi_calibration: hsi-calibration { 159 compatible = "st,hsi-cal"; 160 st,cal_hsi_dev = <31>; 161 st,cal_hsi_ref = <1953>; 162 status = "disabled"; 163 }; 164 165 msi_calibration: msi-calibration { 166 compatible = "st,msi-cal"; 167 status = "disabled"; 168 }; 169 }; 170 171 pinctrl: pinctrl@44240000 { 172 #address-cells = <1>; 173 #size-cells = <1>; 174 compatible = "st,stm32mp257-pinctrl"; 175 ranges = <0 0x44240000 0xa0400>; 176 pins-are-numbered; 177 178 gpioa: gpio@44240000 { 179 gpio-controller; 180 #gpio-cells = <2>; 181 interrupt-controller; 182 #interrupt-cells = <2>; 183 reg = <0x0 0x400>; 184 clocks = <&rcc CK_BUS_GPIOA>; 185 st,bank-name = "GPIOA"; 186 status = "disabled"; 187 }; 188 189 gpiob: gpio@44250000 { 190 gpio-controller; 191 #gpio-cells = <2>; 192 interrupt-controller; 193 #interrupt-cells = <2>; 194 reg = <0x10000 0x400>; 195 clocks = <&rcc CK_BUS_GPIOB>; 196 st,bank-name = "GPIOB"; 197 status = "disabled"; 198 }; 199 200 gpioc: gpio@44260000 { 201 gpio-controller; 202 #gpio-cells = <2>; 203 interrupt-controller; 204 #interrupt-cells = <2>; 205 reg = <0x20000 0x400>; 206 clocks = <&rcc CK_BUS_GPIOC>; 207 st,bank-name = "GPIOC"; 208 status = "disabled"; 209 }; 210 211 gpiod: gpio@44270000 { 212 gpio-controller; 213 #gpio-cells = <2>; 214 interrupt-controller; 215 #interrupt-cells = <2>; 216 reg = <0x30000 0x400>; 217 clocks = <&rcc CK_BUS_GPIOD>; 218 st,bank-name = "GPIOD"; 219 status = "disabled"; 220 }; 221 222 gpioe: gpio@44280000 { 223 gpio-controller; 224 #gpio-cells = <2>; 225 interrupt-controller; 226 #interrupt-cells = <2>; 227 reg = <0x40000 0x400>; 228 clocks = <&rcc CK_BUS_GPIOE>; 229 st,bank-name = "GPIOE"; 230 status = "disabled"; 231 }; 232 233 gpiof: gpio@44290000 { 234 gpio-controller; 235 #gpio-cells = <2>; 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 reg = <0x50000 0x400>; 239 clocks = <&rcc CK_BUS_GPIOF>; 240 st,bank-name = "GPIOF"; 241 status = "disabled"; 242 }; 243 244 gpiog: gpio@442a0000 { 245 gpio-controller; 246 #gpio-cells = <2>; 247 interrupt-controller; 248 #interrupt-cells = <2>; 249 reg = <0x60000 0x400>; 250 clocks = <&rcc CK_BUS_GPIOG>; 251 st,bank-name = "GPIOG"; 252 status = "disabled"; 253 }; 254 255 gpioh: gpio@442b0000 { 256 gpio-controller; 257 #gpio-cells = <2>; 258 interrupt-controller; 259 #interrupt-cells = <2>; 260 reg = <0x70000 0x400>; 261 clocks = <&rcc CK_BUS_GPIOH>; 262 st,bank-name = "GPIOH"; 263 status = "disabled"; 264 }; 265 266 gpioi: gpio@442c0000 { 267 gpio-controller; 268 #gpio-cells = <2>; 269 interrupt-controller; 270 #interrupt-cells = <2>; 271 reg = <0x80000 0x400>; 272 clocks = <&rcc CK_BUS_GPIOI>; 273 st,bank-name = "GPIOI"; 274 status = "disabled"; 275 }; 276 277 gpioj: gpio@442d0000 { 278 gpio-controller; 279 #gpio-cells = <2>; 280 interrupt-controller; 281 #interrupt-cells = <2>; 282 reg = <0x90000 0x400>; 283 clocks = <&rcc CK_BUS_GPIOJ>; 284 st,bank-name = "GPIOJ"; 285 status = "disabled"; 286 }; 287 288 gpiok: gpio@442e0000 { 289 gpio-controller; 290 #gpio-cells = <2>; 291 interrupt-controller; 292 #interrupt-cells = <2>; 293 reg = <0xa0000 0x400>; 294 clocks = <&rcc CK_BUS_GPIOK>; 295 st,bank-name = "GPIOK"; 296 status = "disabled"; 297 }; 298 }; 299 300 pinctrl_z: pinctrl-z@46200000 { 301 #address-cells = <1>; 302 #size-cells = <1>; 303 compatible = "st,stm32mp257-z-pinctrl"; 304 ranges = <0 0x46200000 0x400>; 305 pins-are-numbered; 306 307 gpioz: gpio@46200000 { 308 gpio-controller; 309 #gpio-cells = <2>; 310 interrupt-controller; 311 #interrupt-cells = <2>; 312 reg = <0 0x400>; 313 clocks = <&rcc CK_BUS_GPIOZ>; 314 st,bank-name = "GPIOZ"; 315 st,bank-ioport = <11>; 316 status = "disabled"; 317 }; 318 }; 319 320 hsem: hwspinlock@46240000 { 321 compatible = "st,stm32mp25-hsem"; 322 reg = <0x46240000 0x400>; 323 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 324 status = "disabled"; 325 }; 326 327 ipcc2: mailbox@46250000 { 328 compatible = "st,stm32mp25-ipcc"; 329 reg = <0x46250000 0x400>; 330 status = "disabled"; 331 }; 332 333 fmc: memory-controller@48200000 { 334 #address-cells = <2>; 335 #size-cells = <1>; 336 compatible = "st,stm32mp25-fmc2-ebi"; 337 reg = <0x48200000 0x400>; 338 status = "disabled"; 339 340 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 341 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 342 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 343 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 344 <4 0 0x80000000 0x10000000>; /* NAND */ 345 }; 346 }; 347}; 348