1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 #address-cells = <2>; 11 #size-cells = <2>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "arm,cortex-a35"; 19 device_type = "cpu"; 20 reg = <0>; 21 enable-method = "psci"; 22 }; 23 }; 24 25 psci { 26 compatible = "arm,psci-1.0"; 27 method = "smc"; 28 }; 29 30 intc: interrupt-controller@4ac00000 { 31 compatible = "arm,cortex-a7-gic"; 32 #interrupt-cells = <3>; 33 interrupt-controller; 34 reg = <0x0 0x4ac10000 0x0 0x1000>, 35 <0x0 0x4ac20000 0x0 0x2000>, 36 <0x0 0x4ac40000 0x0 0x2000>, 37 <0x0 0x4ac60000 0x0 0x2000>; 38 #address-cells = <1>; 39 }; 40 41 clocks { 42 clk_hse: clk-hse { 43 #clock-cells = <0>; 44 compatible = "fixed-clock"; 45 clock-frequency = <24000000>; 46 }; 47 48 clk_hsi: clk-hsi { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <64000000>; 52 }; 53 54 clk_lse: clk-lse { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <32768>; 58 }; 59 60 clk_lsi: clk-lsi { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32000>; 64 }; 65 66 clk_msi: clk-msi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <4000000>; 70 }; 71 72 clk_i2sin: clk-i2sin { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <0>; 76 }; 77 78 clocks { 79 clk_rcbsec: clk-rcbsec { 80 #clock-cells = <0>; 81 compatible = "fixed-clock"; 82 clock-frequency = <64000000>; 83 }; 84 }; 85 }; 86 87 soc@0 { 88 compatible = "simple-bus"; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 interrupt-parent = <&intc>; 92 ranges = <0x0 0x0 0x0 0x80000000>; 93 94 rifsc: rifsc@42080000 { 95 compatible = "st,stm32mp25-rifsc"; 96 reg = <0x42080000 0x1000>; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 100 usart2: serial@400e0000 { 101 reg = <0x400e0000 0x400>; 102 status = "disabled"; 103 }; 104 }; 105 106 pinctrl: pinctrl@44240000 { 107 #address-cells = <1>; 108 #size-cells = <1>; 109 compatible = "st,stm32mp257-pinctrl"; 110 ranges = <0 0x44240000 0xa0400>; 111 pins-are-numbered; 112 113 gpioa: gpio@44240000 { 114 gpio-controller; 115 #gpio-cells = <2>; 116 interrupt-controller; 117 #interrupt-cells = <2>; 118 reg = <0x0 0x400>; 119 st,bank-name = "GPIOA"; 120 status = "disabled"; 121 }; 122 123 gpiob: gpio@44250000 { 124 gpio-controller; 125 #gpio-cells = <2>; 126 interrupt-controller; 127 #interrupt-cells = <2>; 128 reg = <0x10000 0x400>; 129 st,bank-name = "GPIOB"; 130 status = "disabled"; 131 }; 132 133 gpioc: gpio@44260000 { 134 gpio-controller; 135 #gpio-cells = <2>; 136 interrupt-controller; 137 #interrupt-cells = <2>; 138 reg = <0x20000 0x400>; 139 st,bank-name = "GPIOC"; 140 status = "disabled"; 141 }; 142 143 gpiod: gpio@44270000 { 144 gpio-controller; 145 #gpio-cells = <2>; 146 interrupt-controller; 147 #interrupt-cells = <2>; 148 reg = <0x30000 0x400>; 149 st,bank-name = "GPIOD"; 150 status = "disabled"; 151 }; 152 153 gpioe: gpio@44280000 { 154 gpio-controller; 155 #gpio-cells = <2>; 156 interrupt-controller; 157 #interrupt-cells = <2>; 158 reg = <0x40000 0x400>; 159 st,bank-name = "GPIOE"; 160 status = "disabled"; 161 }; 162 163 gpiof: gpio@44290000 { 164 gpio-controller; 165 #gpio-cells = <2>; 166 interrupt-controller; 167 #interrupt-cells = <2>; 168 reg = <0x50000 0x400>; 169 st,bank-name = "GPIOF"; 170 status = "disabled"; 171 }; 172 173 gpiog: gpio@442a0000 { 174 gpio-controller; 175 #gpio-cells = <2>; 176 interrupt-controller; 177 #interrupt-cells = <2>; 178 reg = <0x60000 0x400>; 179 st,bank-name = "GPIOG"; 180 status = "disabled"; 181 }; 182 183 gpioh: gpio@442b0000 { 184 gpio-controller; 185 #gpio-cells = <2>; 186 interrupt-controller; 187 #interrupt-cells = <2>; 188 reg = <0x70000 0x400>; 189 st,bank-name = "GPIOH"; 190 status = "disabled"; 191 }; 192 193 gpioi: gpio@442c0000 { 194 gpio-controller; 195 #gpio-cells = <2>; 196 interrupt-controller; 197 #interrupt-cells = <2>; 198 reg = <0x80000 0x400>; 199 st,bank-name = "GPIOI"; 200 status = "disabled"; 201 }; 202 203 gpioj: gpio@442d0000 { 204 gpio-controller; 205 #gpio-cells = <2>; 206 interrupt-controller; 207 #interrupt-cells = <2>; 208 reg = <0x90000 0x400>; 209 st,bank-name = "GPIOJ"; 210 status = "disabled"; 211 }; 212 213 gpiok: gpio@442e0000 { 214 gpio-controller; 215 #gpio-cells = <2>; 216 interrupt-controller; 217 #interrupt-cells = <2>; 218 reg = <0xa0000 0x400>; 219 st,bank-name = "GPIOK"; 220 status = "disabled"; 221 }; 222 }; 223 224 pinctrl_z: pinctrl-z@46200000 { 225 #address-cells = <1>; 226 #size-cells = <1>; 227 compatible = "st,stm32mp257-z-pinctrl"; 228 ranges = <0 0x46200000 0x400>; 229 pins-are-numbered; 230 231 gpioz: gpio@46200000 { 232 gpio-controller; 233 #gpio-cells = <2>; 234 interrupt-controller; 235 #interrupt-cells = <2>; 236 reg = <0 0x400>; 237 st,bank-name = "GPIOZ"; 238 st,bank-ioport = <11>; 239 status = "disabled"; 240 }; 241 }; 242 }; 243}; 244