1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2/* 3 * Copyright (C) 2025, STMicroelectronics - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/st,stm32mp25-rcc.h> 8#include <dt-bindings/firewall/stm32mp25-rif.h> 9#include <dt-bindings/firewall/stm32mp25-rifsc.h> 10#include <dt-bindings/firewall/stm32mp25-risab.h> 11#include <dt-bindings/firewall/stm32mp25-risaf.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/st,stm32mp25-rcc.h> 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a35"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 }; 30 31 psci { 32 compatible = "arm,psci-1.0"; 33 method = "smc"; 34 }; 35 36 intc: interrupt-controller@4ac00000 { 37 compatible = "arm,cortex-a7-gic"; 38 #interrupt-cells = <3>; 39 interrupt-controller; 40 reg = <0x0 0x4ac10000 0x0 0x1000>, 41 <0x0 0x4ac20000 0x0 0x2000>, 42 <0x0 0x4ac40000 0x0 0x2000>, 43 <0x0 0x4ac60000 0x0 0x2000>; 44 #address-cells = <1>; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_msi: clk-msi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <0>; 82 }; 83 84 clk_rcbsec: clk-rcbsec { 85 #clock-cells = <0>; 86 compatible = "fixed-clock"; 87 clock-frequency = <64000000>; 88 }; 89 }; 90 91 soc@0 { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 interrupt-parent = <&intc>; 96 ranges = <0x0 0x0 0x0 0x80000000>; 97 98 hpdma1: dma-controller@40400000 { 99 compatible = "st,stm32-dma3"; 100 reg = <0x40400000 0x1000>; 101 clocks = <&rcc CK_BUS_HPDMA1>; 102 resets = <&rcc HPDMA1_R>; 103 #dma-cells = <4>; 104 status = "disabled"; 105 }; 106 107 hpdma2: dma-controller@40410000 { 108 compatible = "st,stm32-dma3"; 109 reg = <0x40410000 0x1000>; 110 clocks = <&rcc CK_BUS_HPDMA2>; 111 resets = <&rcc HPDMA2_R>; 112 #dma-cells = <4>; 113 status = "disabled"; 114 }; 115 116 hpdma3: dma-controller@40420000 { 117 compatible = "st,stm32-dma3"; 118 reg = <0x40420000 0x1000>; 119 clocks = <&rcc CK_BUS_HPDMA3>; 120 resets = <&rcc HPDMA3_R>; 121 #dma-cells = <4>; 122 status = "disabled"; 123 }; 124 125 ipcc1: mailbox@40490000 { 126 compatible = "st,stm32mp25-ipcc"; 127 reg = <0x40490000 0x400>; 128 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 129 interrupt-names = "rx"; 130 clocks = <&rcc CK_BUS_IPCC1>; 131 status = "disabled"; 132 }; 133 134 ommanager: ommanager@40500000 { 135 compatible = "st,stm32mp25-omm"; 136 reg = <0x40500000 0x400>, <0x60000000 0x10000000>; 137 reg-names = "regs", "memory_map"; 138 ranges = <0 0 0x40430000 0x400>, 139 <1 0 0x40440000 0x400>; 140 clocks = <&rcc CK_BUS_OSPIIOM>; 141 resets = <&rcc OSPIIOM_R>; 142 #address-cells = <2>; 143 #size-cells = <1>; 144 st,syscfg-amcr = <&syscfg 0x2c00 0x7>; 145 status = "disabled"; 146 147 ospi1: spi@0 { 148 compatible = "st,stm32mp25-ospi"; 149 reg = <0 0 0x400>; 150 clocks = <&rcc CK_KER_OSPI1>; 151 resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>; 152 status = "disabled"; 153 }; 154 155 ospi2: spi@1 { 156 compatible = "st,stm32mp25-ospi"; 157 reg = <1 0 0x400>; 158 clocks = <&rcc CK_KER_OSPI2>; 159 resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>; 160 status = "disabled"; 161 }; 162 }; 163 164 rifsc: bus@42080000 { 165 compatible = "st,stm32mp25-rifsc", "simple-bus"; 166 reg = <0x42080000 0x1000>; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 #access-controller-cells = <1>; 170 171 usart2: serial@400e0000 { 172 compatible = "st,stm32h7-uart"; 173 reg = <0x400e0000 0x400>; 174 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&rcc CK_KER_USART2>; 176 access-controllers = <&rifsc STM32MP25_RIFSC_USART2_ID>; 177 status = "disabled"; 178 }; 179 180 rng: rng@42020000 { 181 compatible = "st,stm32mp25-rng"; 182 reg = <0x42020000 0x400>; 183 clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; 184 clock-names = "rng_clk", "rng_hclk"; 185 resets = <&rcc RNG_R>; 186 access-controllers = <&rifsc STM32MP25_RIFSC_RNG_ID>; 187 }; 188 189 iwdg1: watchdog@44010000 { 190 compatible = "st,stm32mp1-iwdg"; 191 reg = <0x44010000 0x400>; 192 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>; 194 clock-names = "pclk", "lsi"; 195 access-controllers = <&rifsc STM32MP25_RIFSC_IWDG1_ID>; 196 status = "disabled"; 197 }; 198 199 iwdg2: watchdog@44020000 { 200 compatible = "st,stm32mp1-iwdg"; 201 reg = <0x44020000 0x400>; 202 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&rcc CK_BUS_IWDG2>, <&rcc LSI_CK>; 204 clock-names = "pclk", "lsi"; 205 resets = <&rcc IWDG2_SYS_R>; 206 access-controllers = <&rifsc STM32MP25_RIFSC_IWDG2_ID>; 207 status = "disabled"; 208 }; 209 }; 210 211 iac: iac@42090000 { 212 compatible = "st,stm32mp25-iac"; 213 reg = <0x42090000 0x400>; 214 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 215 }; 216 217 risaf1: risaf@420a0000 { 218 compatible = "st,stm32mp25-risaf"; 219 reg = <0x420a0000 0x1000>; 220 clocks = <&rcc CK_BUS_BKPSRAM>; 221 st,mem-map = <0x0 0x42000000 0x0 0x2000>; 222 #access-controller-cells = <1>; 223 }; 224 225 risaf2: risaf@420b0000 { 226 compatible = "st,stm32mp25-risaf"; 227 reg = <0x420b0000 0x1000>; 228 clocks = <&rcc CK_KER_OSPI1>; 229 st,mem-map = <0x0 0x60000000 0x0 0x10000000>; 230 #access-controller-cells = <1>; 231 status = "disabled"; 232 }; 233 234 risaf4: risaf@420d0000 { 235 compatible = "st,stm32mp25-risaf-enc"; 236 reg = <0x420d0000 0x1000>; 237 clocks = <&rcc CK_BUS_RISAF4>; 238 st,mem-map = <0x0 0x80000000 0x1 0x00000000>; 239 #access-controller-cells = <1>; 240 }; 241 242 risab1: risab@420f0000 { 243 compatible = "st,stm32mp25-risab"; 244 reg = <0x420f0000 0x1000>; 245 clocks = <&rcc CK_ICN_LS_MCU>; 246 st,mem-map = <0xa000000 0x20000>; 247 #access-controller-cells = <1>; 248 }; 249 250 risab2: risab@42100000 { 251 compatible = "st,stm32mp25-risab"; 252 reg = <0x42100000 0x1000>; 253 clocks = <&rcc CK_ICN_LS_MCU>; 254 st,mem-map = <0xa020000 0x20000>; 255 #access-controller-cells = <1>; 256 }; 257 258 risab3: risab@42110000 { 259 compatible = "st,stm32mp25-risab"; 260 reg = <0x42110000 0x1000>; 261 clocks = <&rcc CK_ICN_LS_MCU>; 262 st,mem-map = <0xa040000 0x20000>; 263 #access-controller-cells = <1>; 264 }; 265 266 risab4: risab@42120000 { 267 compatible = "st,stm32mp25-risab"; 268 reg = <0x42120000 0x1000>; 269 clocks = <&rcc CK_ICN_LS_MCU>; 270 st,mem-map = <0xa060000 0x20000>; 271 #access-controller-cells = <1>; 272 }; 273 274 risab5: risab@42130000 { 275 compatible = "st,stm32mp25-risab"; 276 reg = <0x42130000 0x1000>; 277 clocks = <&rcc CK_ICN_LS_MCU>; 278 st,mem-map = <0xa080000 0x20000>; 279 #access-controller-cells = <1>; 280 }; 281 282 risab6: risab@42140000 { 283 compatible = "st,stm32mp25-risab"; 284 reg = <0x42140000 0x1000>; 285 clocks = <&rcc CK_ICN_LS_MCU>; 286 st,mem-map = <0xa0a0000 0x20000>; 287 #access-controller-cells = <1>; 288 status = "disabled"; 289 }; 290 291 serc: serc@44080000 { 292 compatible = "st,stm32mp25-serc"; 293 reg = <0x44080000 0x1000>; 294 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&rcc CK_BUS_SERC>; 296 }; 297 298 rcc: rcc@44200000 { 299 compatible = "st,stm32mp25-rcc", "syscon"; 300 reg = <0x44200000 0x10000>; 301 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 302 303 #clock-cells = <1>; 304 #reset-cells = <1>; 305 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, 306 <&clk_lsi>, <&clk_msi>, <&clk_i2sin>; 307 clock-names = "clk-hse", "clk-hsi", "clk-lse", 308 "clk-lsi", "clk-msi", "clk-i2sin"; 309 310 hsi_calibration: hsi-calibration { 311 compatible = "st,hsi-cal"; 312 st,cal_hsi_dev = <31>; 313 st,cal_hsi_ref = <1953>; 314 status = "disabled"; 315 }; 316 317 msi_calibration: msi-calibration { 318 compatible = "st,msi-cal"; 319 status = "disabled"; 320 }; 321 }; 322 323 exti1: interrupt-controller@44220000 { 324 compatible = "st,stm32mp1-exti"; 325 interrupt-controller; 326 #interrupt-cells = <2>; 327 reg = <0x44220000 0x400>; 328 interrupts-extended = 329 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 330 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 331 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 332 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 333 <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 334 <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 335 <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 336 <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 337 <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 338 <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 339 <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 340 <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 341 <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 342 <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 343 <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 344 <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 345 <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 346 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 347 <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 348 <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 349 <0>, /* EXTI_20 */ 350 <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 351 <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 352 <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 353 <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 354 <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 355 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 356 <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 357 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 358 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 359 <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 360 <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 361 <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 362 <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 363 <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 364 <0>, 365 <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 366 <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 367 <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 368 <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 369 <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 370 <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 371 <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 372 <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 373 <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 374 <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 375 <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 376 <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 377 <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 378 <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 379 <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 380 <0>, 381 <0>, 382 <0>, 383 <0>, 384 <0>, 385 <0>, 386 <0>, 387 <0>, 388 <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 389 <0>, /* EXTI_60 */ 390 <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 391 <0>, 392 <0>, 393 <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 394 <0>, 395 <0>, 396 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 397 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 398 <0>, 399 <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ 400 <0>, 401 <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 402 <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 403 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 404 <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 405 <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 406 <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 407 <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 408 <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 409 <0>, /* EXTI_80 */ 410 <0>, 411 <0>, 412 <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 413 <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 414 }; 415 416 syscfg: syscon@44230000 { 417 reg = <0x44230000 0x10000>; 418 status = "disabled"; 419 }; 420 421 pinctrl: pinctrl@44240000 { 422 #address-cells = <1>; 423 #size-cells = <1>; 424 compatible = "st,stm32mp257-pinctrl"; 425 ranges = <0 0x44240000 0xa0400>; 426 427 gpioa: gpio@44240000 { 428 gpio-controller; 429 #gpio-cells = <2>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 #access-controller-cells = <1>; 433 reg = <0x0 0x400>; 434 clocks = <&rcc CK_BUS_GPIOA>; 435 st,bank-name = "GPIOA"; 436 status = "disabled"; 437 }; 438 439 gpiob: gpio@44250000 { 440 gpio-controller; 441 #gpio-cells = <2>; 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 #access-controller-cells = <1>; 445 reg = <0x10000 0x400>; 446 clocks = <&rcc CK_BUS_GPIOB>; 447 st,bank-name = "GPIOB"; 448 status = "disabled"; 449 }; 450 451 gpioc: gpio@44260000 { 452 gpio-controller; 453 #gpio-cells = <2>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 #access-controller-cells = <1>; 457 reg = <0x20000 0x400>; 458 clocks = <&rcc CK_BUS_GPIOC>; 459 st,bank-name = "GPIOC"; 460 status = "disabled"; 461 }; 462 463 gpiod: gpio@44270000 { 464 gpio-controller; 465 #gpio-cells = <2>; 466 interrupt-controller; 467 #interrupt-cells = <2>; 468 #access-controller-cells = <1>; 469 reg = <0x30000 0x400>; 470 clocks = <&rcc CK_BUS_GPIOD>; 471 st,bank-name = "GPIOD"; 472 status = "disabled"; 473 }; 474 475 gpioe: gpio@44280000 { 476 gpio-controller; 477 #gpio-cells = <2>; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 #access-controller-cells = <1>; 481 reg = <0x40000 0x400>; 482 clocks = <&rcc CK_BUS_GPIOE>; 483 st,bank-name = "GPIOE"; 484 status = "disabled"; 485 }; 486 487 gpiof: gpio@44290000 { 488 gpio-controller; 489 #gpio-cells = <2>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 #access-controller-cells = <1>; 493 reg = <0x50000 0x400>; 494 clocks = <&rcc CK_BUS_GPIOF>; 495 st,bank-name = "GPIOF"; 496 status = "disabled"; 497 }; 498 499 gpiog: gpio@442a0000 { 500 gpio-controller; 501 #gpio-cells = <2>; 502 interrupt-controller; 503 #interrupt-cells = <2>; 504 #access-controller-cells = <1>; 505 reg = <0x60000 0x400>; 506 clocks = <&rcc CK_BUS_GPIOG>; 507 st,bank-name = "GPIOG"; 508 status = "disabled"; 509 }; 510 511 gpioh: gpio@442b0000 { 512 gpio-controller; 513 #gpio-cells = <2>; 514 interrupt-controller; 515 #interrupt-cells = <2>; 516 #access-controller-cells = <1>; 517 reg = <0x70000 0x400>; 518 clocks = <&rcc CK_BUS_GPIOH>; 519 st,bank-name = "GPIOH"; 520 status = "disabled"; 521 }; 522 523 gpioi: gpio@442c0000 { 524 gpio-controller; 525 #gpio-cells = <2>; 526 interrupt-controller; 527 #interrupt-cells = <2>; 528 #access-controller-cells = <1>; 529 reg = <0x80000 0x400>; 530 clocks = <&rcc CK_BUS_GPIOI>; 531 st,bank-name = "GPIOI"; 532 status = "disabled"; 533 }; 534 }; 535 536 rtc: rtc@46000000 { 537 compatible = "st,stm32mp25-rtc"; 538 reg = <0x46000000 0x400>; 539 clocks = <&rcc CK_BUS_RTC>, <&rcc RTC_CK>; 540 clock-names = "pclk", "rtc_ck"; 541 wakeup-source; 542 interrupts-extended = <&exti2 22 IRQ_TYPE_EDGE_RISING>; 543 }; 544 545 tamp: tamp@46010000 { 546 compatible = "st,stm32mp23-tamp"; 547 reg = <0x46010000 0x400>; 548 clocks = <&rcc CK_BUS_RTC>; 549 interrupts-extended = <&exti2 21 IRQ_TYPE_EDGE_RISING>; 550 #address-cells = <1>; 551 #size-cells = <1>; 552 ranges; 553 st,backup-zones = <24 24 24 24 12 12 8>; 554 }; 555 556 pinctrl_z: pinctrl-z@46200000 { 557 #address-cells = <1>; 558 #size-cells = <1>; 559 compatible = "st,stm32mp257-z-pinctrl"; 560 ranges = <0 0x46200000 0x400>; 561 562 gpioz: gpio@46200000 { 563 gpio-controller; 564 #gpio-cells = <2>; 565 interrupt-controller; 566 #interrupt-cells = <2>; 567 #access-controller-cells = <1>; 568 reg = <0 0x400>; 569 clocks = <&rcc CK_BUS_GPIOZ>; 570 st,bank-name = "GPIOZ"; 571 st,bank-ioport = <11>; 572 status = "disabled"; 573 }; 574 }; 575 576 exti2: interrupt-controller@46230000 { 577 compatible = "st,stm32mp1-exti"; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 reg = <0x46230000 0x400>; 581 interrupts-extended = 582 <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 583 <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 584 <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 585 <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 586 <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 587 <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 588 <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 589 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 590 <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 591 <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 592 <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 593 <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 594 <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 595 <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 596 <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 597 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 598 <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 599 <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 600 <0>, 601 <0>, 602 <0>, /* EXTI_20 */ 603 <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 604 <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 605 <0>, 606 <0>, 607 <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 608 <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 609 <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 610 <0>, 611 <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 612 <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 613 <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 614 <0>, 615 <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 616 <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 617 <0>, 618 <0>, 619 <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 620 <0>, 621 <0>, 622 <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ 623 <0>, 624 <0>, 625 <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 626 <0>, 627 <0>, 628 <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 629 <0>, 630 <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 631 <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 632 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 633 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 634 <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 635 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 636 <0>, 637 <0>, 638 <0>, 639 <0>, 640 <0>, 641 <0>, 642 <0>, /* EXTI_60 */ 643 <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 644 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 645 <0>, 646 <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 647 <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 648 <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 649 <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 650 <0>, 651 <0>, 652 <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 653 }; 654 655 hsem: hwspinlock@46240000 { 656 compatible = "st,stm32mp25-hsem"; 657 reg = <0x46240000 0x400>; 658 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&rcc CK_BUS_HSEM>; 660 }; 661 662 stgenc: stgen@48080000 { 663 compatible = "st,stm32mp25-stgen"; 664 reg = <0x48080000 0x1000>; 665 clocks = <&rcc CK_BUS_STGEN>, <&rcc CK_KER_STGEN>; 666 clock-names = "bus", "stgen_clk"; 667 }; 668 669 fmc: memory-controller@48200000 { 670 compatible = "st,stm32mp25-fmc2-ebi"; 671 reg = <0x48200000 0x400>; 672 ranges = <0 0 0x70000000 0x04000000>, /* EBI CS 1 */ 673 <1 0 0x74000000 0x04000000>, /* EBI CS 2 */ 674 <2 0 0x78000000 0x04000000>, /* EBI CS 3 */ 675 <3 0 0x7c000000 0x04000000>, /* EBI CS 4 */ 676 <4 0 0x48810000 0x00001000>; /* NAND */ 677 #address-cells = <2>; 678 #size-cells = <1>; 679 clocks = <&rcc CK_KER_FMC>; 680 resets = <&rcc FMC_R>; 681 status = "disabled"; 682 }; 683 }; 684}; 685