1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/firewall/stm32mp13-etzpc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include <dt-bindings/reset/stm32mp13-resets.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a7"; 24 device_type = "cpu"; 25 reg = <0>; 26 clocks = <&rcc CK_MPU>; 27 clock-names = "cpu"; 28 operating-points-v2 = <&cpu0_opp_table>; 29 nvmem-cells = <&part_number_otp>; 30 nvmem-cell-names = "part_number"; 31 }; 32 }; 33 34 cpu0_opp_table: cpu0-opp-table { 35 compatible = "operating-points-v2"; 36 37 /* Non‑overdrive OPP mission profile */ 38 opp-650000000 { 39 opp-hz = /bits/ 64 <650000000>; 40 opp-microvolt = <1250000>; 41 opp-supported-hw = <0x3>; 42 st,opp-default; 43 }; 44 45 /* Overdrive OPP: 10‑year life activity @100% activity rate */ 46 opp-900000000 { 47 opp-hz = /bits/ 64 <900000000>; 48 opp-microvolt = <1350000>; 49 opp-supported-hw = <0x2>; 50 st,opp-default; 51 }; 52 53 /* Overdrive OPP: 10‑year life activity @25% activity rate */ 54 opp-1000000000 { 55 opp-hz = /bits/ 64 <1000000000>; 56 opp-microvolt = <1350000>; 57 opp-supported-hw = <0x2>; 58 }; 59 }; 60 61 hse_monitor: hse-monitor { 62 compatible = "st,freq-monitor"; 63 counter = <&lptimer3 1 1 0 0>; 64 status = "disabled"; 65 }; 66 67 intc: interrupt-controller@a0021000 { 68 compatible = "arm,cortex-a7-gic"; 69 #interrupt-cells = <3>; 70 interrupt-controller; 71 reg = <0xa0021000 0x1000>, 72 <0xa0022000 0x2000>; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0"; 77 method = "smc"; 78 }; 79 80 clocks { 81 clk_hse: clk-hse { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <24000000>; 85 }; 86 87 clk_hsi: clk-hsi { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <64000000>; 91 }; 92 93 clk_lse: clk-lse { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <32768>; 97 }; 98 99 clk_lsi: clk-lsi { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <32000>; 103 }; 104 105 clk_csi: clk-csi { 106 #clock-cells = <0>; 107 compatible = "fixed-clock"; 108 clock-frequency = <4000000>; 109 }; 110 111 clk_i2sin: clk-i2sin { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <19000000>; 115 }; 116 117 }; 118 119 sdmmc1_io: sdmmc1_io { 120 compatible = "st,stm32mp13-iod"; 121 regulator-name = "sdmmc1_io"; 122 regulator-always-on; 123 }; 124 125 sdmmc2_io: sdmmc2_io { 126 compatible = "st,stm32mp13-iod"; 127 regulator-name = "sdmmc2_io"; 128 regulator-always-on; 129 }; 130 131 soc { 132 compatible = "simple-bus"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 interrupt-parent = <&intc>; 136 ranges; 137 138 usart3: serial@4000f000 { 139 compatible = "st,stm32h7-uart"; 140 reg = <0x4000f000 0x400>; 141 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&rcc USART3_K>; 143 resets = <&rcc USART3_R>; 144 status = "disabled"; 145 }; 146 147 uart4: serial@40010000 { 148 compatible = "st,stm32h7-uart"; 149 reg = <0x40010000 0x400>; 150 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&rcc UART4_K>; 152 resets = <&rcc UART4_R>; 153 status = "disabled"; 154 }; 155 156 uart5: serial@40011000 { 157 compatible = "st,stm32h7-uart"; 158 reg = <0x40011000 0x400>; 159 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&rcc UART5_K>; 161 resets = <&rcc UART5_R>; 162 status = "disabled"; 163 }; 164 165 uart7: serial@40018000 { 166 compatible = "st,stm32h7-uart"; 167 reg = <0x40018000 0x400>; 168 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&rcc UART7_K>; 170 resets = <&rcc UART7_R>; 171 status = "disabled"; 172 }; 173 174 uart8: serial@40019000 { 175 compatible = "st,stm32h7-uart"; 176 reg = <0x40019000 0x400>; 177 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 178 clocks = <&rcc UART8_K>; 179 resets = <&rcc UART8_R>; 180 status = "disabled"; 181 }; 182 183 usart6: serial@44003000 { 184 compatible = "st,stm32h7-uart"; 185 reg = <0x44003000 0x400>; 186 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&rcc USART6_K>; 188 resets = <&rcc USART6_R>; 189 status = "disabled"; 190 }; 191 192 rcc: rcc@50000000 { 193 compatible = "st,stm32mp13-rcc", "syscon"; 194 reg = <0x50000000 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 #clock-cells = <1>; 198 #reset-cells = <1>; 199 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 200 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 201 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 202 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 203 secure-interrupt-names = "wakeup"; 204 }; 205 206 pwr_regulators: pwr@50001000 { 207 compatible = "st,stm32mp1,pwr-reg"; 208 reg = <0x50001000 0x10>; 209 210 reg11: reg11 { 211 regulator-name = "reg11"; 212 regulator-min-microvolt = <1100000>; 213 regulator-max-microvolt = <1100000>; 214 }; 215 216 reg18: reg18 { 217 regulator-name = "reg18"; 218 regulator-min-microvolt = <1800000>; 219 regulator-max-microvolt = <1800000>; 220 }; 221 222 usb33: usb33 { 223 regulator-name = "usb33"; 224 regulator-min-microvolt = <3300000>; 225 regulator-max-microvolt = <3300000>; 226 }; 227 }; 228 229 pwr_irq: pwr@50001010 { 230 compatible = "st,stm32mp1,pwr-irq"; 231 status = "disabled"; 232 }; 233 234 exti: interrupt-controller@5000d000 { 235 compatible = "st,stm32mp1-exti"; 236 interrupt-controller; 237 #interrupt-cells = <2>; 238 reg = <0x5000d000 0x400>; 239 interrupts-extended = 240 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 241 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 242 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 243 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 244 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 245 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 246 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 247 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 248 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 249 <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 250 <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 251 <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 252 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 253 <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 254 <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 255 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 256 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 257 <0>, 258 <&intc GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 259 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 260 <0>, /* EXTI_20 */ 261 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 262 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 263 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 264 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 265 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 266 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 267 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 268 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 269 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 270 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 271 <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 272 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 273 <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 274 <0>, 275 <0>, 276 <0>, 277 <0>, 278 <0>, 279 <0>, 280 <0>, /* EXTI_40 */ 281 <0>, 282 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 283 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 284 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 285 <0>, 286 <0>, 287 <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 288 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 289 <0>, 290 <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 291 <0>, 292 <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 293 <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 294 <0>, 295 <0>, 296 <0>, 297 <0>, 298 <0>, 299 <0>, 300 <0>, /* EXTI_60 */ 301 <0>, 302 <0>, 303 <0>, 304 <0>, 305 <0>, 306 <0>, 307 <0>, 308 <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 309 <0>, 310 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 311 }; 312 313 syscfg: syscon@50020000 { 314 compatible = "st,stm32mp157-syscfg", "syscon"; 315 reg = <0x50020000 0x400>; 316 }; 317 318 iwdg2: watchdog@5a002000 { 319 compatible = "st,stm32mp1-iwdg"; 320 reg = <0x5a002000 0x400>; 321 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 323 clock-names = "pclk", "lsi"; 324 status = "disabled"; 325 }; 326 327 rtc: rtc@5c004000 { 328 compatible = "st,stm32mp13-rtc"; 329 reg = <0x5c004000 0x400>; 330 clocks = <&rcc RTCAPB>, <&rcc RTC>; 331 clock-names = "pclk", "rtc_ck"; 332 status = "disabled"; 333 }; 334 335 bsec: efuse@5c005000 { 336 compatible = "st,stm32mp13-bsec"; 337 reg = <0x5c005000 0x400>; 338 #address-cells = <1>; 339 #size-cells = <1>; 340 341 cfg0_otp: cfg0_otp@0 { 342 reg = <0x0 0x2>; 343 }; 344 part_number_otp: part_number_otp@4 { 345 reg = <0x4 0x2>; 346 bits = <0 12>; 347 }; 348 monotonic_otp: monotonic_otp@10 { 349 reg = <0x10 0x4>; 350 }; 351 nand_otp: cfg9_otp@24 { 352 reg = <0x24 0x4>; 353 }; 354 uid_otp: uid_otp@34 { 355 reg = <0x34 0xc>; 356 }; 357 hw2_otp: hw2_otp@48 { 358 reg = <0x48 0x4>; 359 }; 360 ts_cal1: calib@5c { 361 reg = <0x5c 0x2>; 362 }; 363 ts_cal2: calib@5e { 364 reg = <0x5e 0x2>; 365 }; 366 pkh_otp: pkh_otp@60 { 367 reg = <0x60 0x20>; 368 }; 369 ethernet_mac1_address: mac1@e4 { 370 reg = <0xe4 0xc>; 371 st,non-secure-otp; 372 }; 373 oem_enc_key: oem_enc_key@170 { 374 reg = <0x170 0x10>; 375 }; 376 }; 377 378 tzc400: tzc@5c006000 { 379 compatible = "st,stm32mp1-tzc"; 380 reg = <0x5c006000 0x1000>; 381 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 382 st,mem-map = <0xc0000000 0x40000000>; 383 clocks = <&rcc TZC>; 384 }; 385 386 tamp: tamp@5c00a000 { 387 compatible = "st,stm32mp13-tamp"; 388 reg = <0x5c00a000 0x400>; 389 interrupts-extended = <&exti 18 IRQ_TYPE_EDGE_RISING>; 390 clocks = <&rcc RTCAPB>; 391 st,backup-zones = <10 5 17>; 392 }; 393 394 pinctrl: pin-controller@50002000 { 395 #address-cells = <1>; 396 #size-cells = <1>; 397 compatible = "st,stm32mp135-pinctrl"; 398 ranges = <0 0x50002000 0x8400>; 399 pins-are-numbered; 400 401 gpioa: gpio@50002000 { 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 #access-controller-cells = <1>; 407 clocks = <&rcc GPIOA>; 408 reg = <0x0 0x400>; 409 st,bank-name = "GPIOA"; 410 ngpios = <16>; 411 gpio-ranges = <&pinctrl 0 0 16>; 412 }; 413 414 gpiob: gpio@50003000 { 415 gpio-controller; 416 #gpio-cells = <2>; 417 interrupt-controller; 418 #interrupt-cells = <2>; 419 #access-controller-cells = <1>; 420 clocks = <&rcc GPIOB>; 421 reg = <0x1000 0x400>; 422 st,bank-name = "GPIOB"; 423 ngpios = <16>; 424 gpio-ranges = <&pinctrl 0 16 16>; 425 }; 426 427 gpioc: gpio@50004000 { 428 gpio-controller; 429 #gpio-cells = <2>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 #access-controller-cells = <1>; 433 clocks = <&rcc GPIOC>; 434 reg = <0x2000 0x400>; 435 st,bank-name = "GPIOC"; 436 ngpios = <16>; 437 gpio-ranges = <&pinctrl 0 32 16>; 438 }; 439 440 gpiod: gpio@50005000 { 441 gpio-controller; 442 #gpio-cells = <2>; 443 interrupt-controller; 444 #interrupt-cells = <2>; 445 #access-controller-cells = <1>; 446 clocks = <&rcc GPIOD>; 447 reg = <0x3000 0x400>; 448 st,bank-name = "GPIOD"; 449 ngpios = <16>; 450 gpio-ranges = <&pinctrl 0 48 16>; 451 }; 452 453 gpioe: gpio@50006000 { 454 gpio-controller; 455 #gpio-cells = <2>; 456 interrupt-controller; 457 #interrupt-cells = <2>; 458 #access-controller-cells = <1>; 459 clocks = <&rcc GPIOE>; 460 reg = <0x4000 0x400>; 461 st,bank-name = "GPIOE"; 462 ngpios = <16>; 463 gpio-ranges = <&pinctrl 0 64 16>; 464 }; 465 466 gpiof: gpio@50007000 { 467 gpio-controller; 468 #gpio-cells = <2>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 #access-controller-cells = <1>; 472 clocks = <&rcc GPIOF>; 473 reg = <0x5000 0x400>; 474 st,bank-name = "GPIOF"; 475 ngpios = <16>; 476 gpio-ranges = <&pinctrl 0 80 16>; 477 }; 478 479 gpiog: gpio@50008000 { 480 gpio-controller; 481 #gpio-cells = <2>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 #access-controller-cells = <1>; 485 clocks = <&rcc GPIOG>; 486 reg = <0x6000 0x400>; 487 st,bank-name = "GPIOG"; 488 ngpios = <16>; 489 gpio-ranges = <&pinctrl 0 96 16>; 490 }; 491 492 gpioh: gpio@50009000 { 493 gpio-controller; 494 #gpio-cells = <2>; 495 interrupt-controller; 496 #interrupt-cells = <2>; 497 #access-controller-cells = <1>; 498 clocks = <&rcc GPIOH>; 499 reg = <0x7000 0x400>; 500 st,bank-name = "GPIOH"; 501 ngpios = <15>; 502 gpio-ranges = <&pinctrl 0 112 15>; 503 }; 504 505 gpioi: gpio@5000a000 { 506 gpio-controller; 507 #gpio-cells = <2>; 508 interrupt-controller; 509 #interrupt-cells = <2>; 510 #access-controller-cells = <1>; 511 clocks = <&rcc GPIOI>; 512 reg = <0x8000 0x400>; 513 st,bank-name = "GPIOI"; 514 ngpios = <8>; 515 gpio-ranges = <&pinctrl 0 128 8>; 516 }; 517 }; 518 519 etzpc: etzpc@5c007000 { 520 compatible = "st,stm32-etzpc", "simple-bus"; 521 reg = <0x5C007000 0x400>; 522 clocks = <&rcc TZPC>; 523 #address-cells = <1>; 524 #size-cells = <1>; 525 #access-controller-cells = <1>; 526 527 adc_2: adc@48004000 { 528 reg = <0x48004000 0x400>; 529 compatible = "st,stm32mp13-adc-core"; 530 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 532 clock-names = "bus", "adc"; 533 interrupt-controller; 534 #interrupt-cells = <1>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; 538 status = "disabled"; 539 540 adc2: adc@0 { 541 compatible = "st,stm32mp13-adc"; 542 reg = <0x0>; 543 #io-channel-cells = <1>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 interrupt-parent = <&adc_2>; 547 interrupts = <0>; 548 status = "disabled"; 549 550 channel@13 { 551 reg = <13>; 552 label = "vrefint"; 553 }; 554 555 channel@14 { 556 reg = <14>; 557 label = "vddcore"; 558 }; 559 560 channel@16 { 561 reg = <16>; 562 label = "vddcpu"; 563 }; 564 565 channel@17 { 566 reg = <17>; 567 label = "vddq_ddr"; 568 }; 569 }; 570 }; 571 572 usart1: serial@4c000000 { 573 compatible = "st,stm32h7-uart"; 574 reg = <0x4c000000 0x400>; 575 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&rcc USART1_K>; 577 resets = <&rcc USART1_R>; 578 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 579 status = "disabled"; 580 }; 581 582 usart2: serial@4c001000 { 583 compatible = "st,stm32h7-uart"; 584 reg = <0x4c001000 0x400>; 585 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&rcc USART2_K>; 587 resets = <&rcc USART2_R>; 588 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 589 status = "disabled"; 590 }; 591 592 i2c3: i2c@4c004000 { 593 compatible = "st,stm32mp13-i2c"; 594 reg = <0x4c004000 0x400>; 595 clocks = <&rcc I2C3_K>; 596 resets = <&rcc I2C3_R>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 st,syscfg-fmp = <&syscfg 0x4 0x4>; 600 i2c-analog-filter; 601 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 602 status = "disabled"; 603 }; 604 605 i2c4: i2c@4c005000 { 606 compatible = "st,stm32mp13-i2c"; 607 reg = <0x4c005000 0x400>; 608 clocks = <&rcc I2C4_K>; 609 resets = <&rcc I2C4_R>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 st,syscfg-fmp = <&syscfg 0x4 0x8>; 613 i2c-analog-filter; 614 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 615 status = "disabled"; 616 }; 617 618 i2c5: i2c@4c006000 { 619 compatible = "st,stm32mp13-i2c"; 620 reg = <0x4c006000 0x400>; 621 clocks = <&rcc I2C5_K>; 622 resets = <&rcc I2C5_R>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 st,syscfg-fmp = <&syscfg 0x4 0x10>; 626 i2c-analog-filter; 627 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 628 status = "disabled"; 629 }; 630 631 timers12: timer@4c007000 { 632 #address-cells = <1>; 633 #size-cells = <0>; 634 compatible = "st,stm32-timers"; 635 reg = <0x4c007000 0x400>; 636 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&rcc TIM12_K>; 638 clock-names = "int"; 639 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 640 status = "disabled"; 641 642 counter { 643 compatible = "st,stm32-timer-counter"; 644 status = "disabled"; 645 }; 646 }; 647 648 timers13: timer@4c008000 { 649 #address-cells = <1>; 650 #size-cells = <0>; 651 compatible = "st,stm32-timers"; 652 reg = <0x4c008000 0x400>; 653 clocks = <&rcc TIM13_K>; 654 clock-names = "int"; 655 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 656 status = "disabled"; 657 }; 658 659 timers14: timer@4c009000 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 compatible = "st,stm32-timers"; 663 reg = <0x4c009000 0x400>; 664 clocks = <&rcc TIM14_K>; 665 clock-names = "int"; 666 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 667 status = "disabled"; 668 }; 669 670 timers15: timer@4c00a000 { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 compatible = "st,stm32-timers"; 674 reg = <0x4c00a000 0x400>; 675 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&rcc TIM15_K>; 677 clock-names = "int"; 678 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 679 status = "disabled"; 680 681 counter { 682 compatible = "st,stm32-timer-counter"; 683 status = "disabled"; 684 }; 685 }; 686 687 timers16: timer@4c00b000 { 688 #address-cells = <1>; 689 #size-cells = <0>; 690 compatible = "st,stm32-timers"; 691 reg = <0x4c00b000 0x400>; 692 clocks = <&rcc TIM16_K>; 693 clock-names = "int"; 694 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 695 status = "disabled"; 696 }; 697 698 timers17: timer@4c00c000 { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 compatible = "st,stm32-timers"; 702 reg = <0x4c00c000 0x400>; 703 clocks = <&rcc TIM17_K>; 704 clock-names = "int"; 705 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 706 status = "disabled"; 707 }; 708 709 lptimer2: timer@50021000 { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 compatible = "st,stm32-lptimer"; 713 reg = <0x50021000 0x400>; 714 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&rcc LPTIM2_K>; 716 clock-names = "mux"; 717 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 718 status = "disabled"; 719 }; 720 721 lptimer3: timer@50022000 { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 compatible = "st,stm32-lptimer"; 725 reg = <0x50022000 0x400>; 726 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&rcc LPTIM3_K>; 728 clock-names = "mux"; 729 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 730 status = "disabled"; 731 732 counter { 733 compatible = "st,stm32-lptimer-counter"; 734 status = "disabled"; 735 }; 736 }; 737 738 vrefbuf: vrefbuf@50025000 { 739 compatible = "st,stm32mp13-vrefbuf"; 740 reg = <0x50025000 0x8>; 741 regulator-name = "vrefbuf"; 742 regulator-min-microvolt = <1650000>; 743 regulator-max-microvolt = <2500000>; 744 clocks = <&rcc VREF>; 745 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 746 status = "disabled"; 747 }; 748 749 hash: hash@54003000 { 750 compatible = "st,stm32mp13-hash"; 751 reg = <0x54003000 0x400>; 752 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&rcc HASH1>; 754 resets = <&rcc HASH1_R>; 755 access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; 756 status = "disabled"; 757 }; 758 759 rng: rng@54004000 { 760 compatible = "st,stm32mp13-rng"; 761 reg = <0x54004000 0x400>; 762 clocks = <&rcc RNG1_K>; 763 resets = <&rcc RNG1_R>; 764 access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; 765 status = "disabled"; 766 }; 767 768 iwdg1: watchdog@5c003000 { 769 compatible = "st,stm32mp1-iwdg"; 770 reg = <0x5C003000 0x400>; 771 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 772 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 773 clock-names = "pclk", "lsi"; 774 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 775 status = "disabled"; 776 }; 777 778 stgen: stgen@5c008000 { 779 compatible = "st,stm32-stgen"; 780 reg = <0x5C008000 0x1000>; 781 access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; 782 }; 783 }; 784 }; 785}; 786