1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 11#include <dt-bindings/reset/stm32mp13-resets.h> 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a7"; 23 device_type = "cpu"; 24 reg = <0>; 25 }; 26 }; 27 28 hse_monitor: hse-monitor { 29 compatible = "st,freq-monitor"; 30 counter = <&lptimer3 1 1 0 0>; 31 status = "disabled"; 32 }; 33 34 intc: interrupt-controller@a0021000 { 35 compatible = "arm,cortex-a7-gic"; 36 #interrupt-cells = <3>; 37 interrupt-controller; 38 reg = <0xa0021000 0x1000>, 39 <0xa0022000 0x2000>; 40 }; 41 42 psci { 43 compatible = "arm,psci-1.0"; 44 method = "smc"; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_csi: clk-csi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <19000000>; 82 }; 83 84 }; 85 86 sdmmc1_io: sdmmc1_io { 87 compatible = "st,stm32mp13-iod"; 88 regulator-name = "sdmmc1_io"; 89 regulator-always-on; 90 }; 91 92 sdmmc2_io: sdmmc2_io { 93 compatible = "st,stm32mp13-iod"; 94 regulator-name = "sdmmc2_io"; 95 regulator-always-on; 96 }; 97 98 soc { 99 compatible = "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 interrupt-parent = <&intc>; 103 ranges; 104 105 usart3: serial@4000f000 { 106 compatible = "st,stm32h7-uart"; 107 reg = <0x4000f000 0x400>; 108 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 109 clocks = <&rcc USART3_K>; 110 resets = <&rcc USART3_R>; 111 status = "disabled"; 112 }; 113 114 uart4: serial@40010000 { 115 compatible = "st,stm32h7-uart"; 116 reg = <0x40010000 0x400>; 117 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 118 clocks = <&rcc UART4_K>; 119 resets = <&rcc UART4_R>; 120 status = "disabled"; 121 }; 122 123 uart5: serial@40011000 { 124 compatible = "st,stm32h7-uart"; 125 reg = <0x40011000 0x400>; 126 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&rcc UART5_K>; 128 resets = <&rcc UART5_R>; 129 status = "disabled"; 130 }; 131 132 uart7: serial@40018000 { 133 compatible = "st,stm32h7-uart"; 134 reg = <0x40018000 0x400>; 135 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 136 clocks = <&rcc UART7_K>; 137 resets = <&rcc UART7_R>; 138 status = "disabled"; 139 }; 140 141 uart8: serial@40019000 { 142 compatible = "st,stm32h7-uart"; 143 reg = <0x40019000 0x400>; 144 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&rcc UART8_K>; 146 resets = <&rcc UART8_R>; 147 status = "disabled"; 148 }; 149 150 usart6: serial@44003000 { 151 compatible = "st,stm32h7-uart"; 152 reg = <0x44003000 0x400>; 153 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&rcc USART6_K>; 155 resets = <&rcc USART6_R>; 156 status = "disabled"; 157 }; 158 159 rcc: rcc@50000000 { 160 compatible = "st,stm32mp13-rcc", "syscon"; 161 reg = <0x50000000 0x1000>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 #clock-cells = <1>; 165 #reset-cells = <1>; 166 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 167 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 168 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 169 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 170 secure-interrupt-names = "wakeup"; 171 }; 172 173 pwr_regulators: pwr@50001000 { 174 compatible = "st,stm32mp1,pwr-reg"; 175 reg = <0x50001000 0x10>; 176 177 reg11: reg11 { 178 regulator-name = "reg11"; 179 regulator-min-microvolt = <1100000>; 180 regulator-max-microvolt = <1100000>; 181 }; 182 183 reg18: reg18 { 184 regulator-name = "reg18"; 185 regulator-min-microvolt = <1800000>; 186 regulator-max-microvolt = <1800000>; 187 }; 188 189 usb33: usb33 { 190 regulator-name = "usb33"; 191 regulator-min-microvolt = <3300000>; 192 regulator-max-microvolt = <3300000>; 193 }; 194 }; 195 196 pwr_irq: pwr@50001010 { 197 compatible = "st,stm32mp1,pwr-irq"; 198 status = "disabled"; 199 }; 200 201 syscfg: syscon@50020000 { 202 compatible = "st,stm32mp157-syscfg", "syscon"; 203 reg = <0x50020000 0x400>; 204 }; 205 206 iwdg2: watchdog@5a002000 { 207 compatible = "st,stm32mp1-iwdg"; 208 reg = <0x5a002000 0x400>; 209 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 211 clock-names = "pclk", "lsi"; 212 status = "disabled"; 213 }; 214 215 rtc: rtc@5c004000 { 216 compatible = "st,stm32mp13-rtc"; 217 reg = <0x5c004000 0x400>; 218 clocks = <&rcc RTCAPB>, <&rcc RTC>; 219 clock-names = "pclk", "rtc_ck"; 220 status = "disabled"; 221 }; 222 223 bsec: efuse@5c005000 { 224 compatible = "st,stm32mp13-bsec"; 225 reg = <0x5c005000 0x400>; 226 #address-cells = <1>; 227 #size-cells = <1>; 228 229 cfg0_otp: cfg0_otp@0 { 230 reg = <0x0 0x2>; 231 }; 232 part_number_otp: part_number_otp@4 { 233 reg = <0x4 0x2>; 234 bits = <0 12>; 235 }; 236 monotonic_otp: monotonic_otp@10 { 237 reg = <0x10 0x4>; 238 }; 239 nand_otp: cfg9_otp@24 { 240 reg = <0x24 0x4>; 241 }; 242 uid_otp: uid_otp@34 { 243 reg = <0x34 0xc>; 244 }; 245 hw2_otp: hw2_otp@48 { 246 reg = <0x48 0x4>; 247 }; 248 ts_cal1: calib@5c { 249 reg = <0x5c 0x2>; 250 }; 251 ts_cal2: calib@5e { 252 reg = <0x5e 0x2>; 253 }; 254 pkh_otp: pkh_otp@60 { 255 reg = <0x60 0x20>; 256 }; 257 ethernet_mac1_address: mac1@e4 { 258 reg = <0xe4 0xc>; 259 st,non-secure-otp; 260 }; 261 oem_enc_key: oem_enc_key@170 { 262 reg = <0x170 0x10>; 263 }; 264 }; 265 266 tzc400: tzc@5c006000 { 267 compatible = "st,stm32mp1-tzc"; 268 reg = <0x5c006000 0x1000>; 269 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 270 st,mem-map = <0xc0000000 0x40000000>; 271 clocks = <&rcc TZC>; 272 }; 273 274 tamp: tamp@5c00a000 { 275 compatible = "st,stm32mp13-tamp"; 276 reg = <0x5c00a000 0x400>; 277 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&rcc RTCAPB>; 279 }; 280 281 pinctrl: pin-controller@50002000 { 282 #address-cells = <1>; 283 #size-cells = <1>; 284 compatible = "st,stm32mp135-pinctrl"; 285 ranges = <0 0x50002000 0x8400>; 286 pins-are-numbered; 287 288 gpioa: gpio@50002000 { 289 gpio-controller; 290 #gpio-cells = <2>; 291 interrupt-controller; 292 #interrupt-cells = <2>; 293 clocks = <&rcc GPIOA>; 294 reg = <0x0 0x400>; 295 st,bank-name = "GPIOA"; 296 ngpios = <16>; 297 gpio-ranges = <&pinctrl 0 0 16>; 298 }; 299 300 gpiob: gpio@50003000 { 301 gpio-controller; 302 #gpio-cells = <2>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 clocks = <&rcc GPIOB>; 306 reg = <0x1000 0x400>; 307 st,bank-name = "GPIOB"; 308 ngpios = <16>; 309 gpio-ranges = <&pinctrl 0 16 16>; 310 }; 311 312 gpioc: gpio@50004000 { 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 clocks = <&rcc GPIOC>; 318 reg = <0x2000 0x400>; 319 st,bank-name = "GPIOC"; 320 ngpios = <16>; 321 gpio-ranges = <&pinctrl 0 32 16>; 322 }; 323 324 gpiod: gpio@50005000 { 325 gpio-controller; 326 #gpio-cells = <2>; 327 interrupt-controller; 328 #interrupt-cells = <2>; 329 clocks = <&rcc GPIOD>; 330 reg = <0x3000 0x400>; 331 st,bank-name = "GPIOD"; 332 ngpios = <16>; 333 gpio-ranges = <&pinctrl 0 48 16>; 334 }; 335 336 gpioe: gpio@50006000 { 337 gpio-controller; 338 #gpio-cells = <2>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 clocks = <&rcc GPIOE>; 342 reg = <0x4000 0x400>; 343 st,bank-name = "GPIOE"; 344 ngpios = <16>; 345 gpio-ranges = <&pinctrl 0 64 16>; 346 }; 347 348 gpiof: gpio@50007000 { 349 gpio-controller; 350 #gpio-cells = <2>; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 clocks = <&rcc GPIOF>; 354 reg = <0x5000 0x400>; 355 st,bank-name = "GPIOF"; 356 ngpios = <16>; 357 gpio-ranges = <&pinctrl 0 80 16>; 358 }; 359 360 gpiog: gpio@50008000 { 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 clocks = <&rcc GPIOG>; 366 reg = <0x6000 0x400>; 367 st,bank-name = "GPIOG"; 368 ngpios = <16>; 369 gpio-ranges = <&pinctrl 0 96 16>; 370 }; 371 372 gpioh: gpio@50009000 { 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 clocks = <&rcc GPIOH>; 378 reg = <0x7000 0x400>; 379 st,bank-name = "GPIOH"; 380 ngpios = <15>; 381 gpio-ranges = <&pinctrl 0 112 15>; 382 }; 383 384 gpioi: gpio@5000a000 { 385 gpio-controller; 386 #gpio-cells = <2>; 387 interrupt-controller; 388 #interrupt-cells = <2>; 389 clocks = <&rcc GPIOI>; 390 reg = <0x8000 0x400>; 391 st,bank-name = "GPIOI"; 392 ngpios = <8>; 393 gpio-ranges = <&pinctrl 0 128 8>; 394 }; 395 }; 396 397 etzpc: etzpc@5c007000 { 398 compatible = "st,stm32-etzpc", "firewall-bus"; 399 reg = <0x5C007000 0x400>; 400 clocks = <&rcc TZPC>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 404 adc_2: adc@48004000 { 405 reg = <0x48004000 0x400>; 406 compatible = "st,stm32mp13-adc-core"; 407 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 409 clock-names = "bus", "adc"; 410 interrupt-controller; 411 #interrupt-cells = <1>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 status = "disabled"; 415 416 adc2: adc@0 { 417 compatible = "st,stm32mp13-adc"; 418 reg = <0x0>; 419 #io-channel-cells = <1>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 interrupt-parent = <&adc_2>; 423 interrupts = <0>; 424 status = "disabled"; 425 426 channel@13 { 427 reg = <13>; 428 label = "vrefint"; 429 }; 430 431 channel@14 { 432 reg = <14>; 433 label = "vddcore"; 434 }; 435 436 channel@16 { 437 reg = <16>; 438 label = "vddcpu"; 439 }; 440 441 channel@17 { 442 reg = <17>; 443 label = "vddq_ddr"; 444 }; 445 }; 446 }; 447 448 usart1: serial@4c000000 { 449 compatible = "st,stm32h7-uart"; 450 reg = <0x4c000000 0x400>; 451 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&rcc USART1_K>; 453 resets = <&rcc USART1_R>; 454 status = "disabled"; 455 }; 456 457 usart2: serial@4c001000 { 458 compatible = "st,stm32h7-uart"; 459 reg = <0x4c001000 0x400>; 460 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&rcc USART2_K>; 462 resets = <&rcc USART2_R>; 463 status = "disabled"; 464 }; 465 466 i2c3: i2c@4c004000 { 467 compatible = "st,stm32mp13-i2c"; 468 reg = <0x4c004000 0x400>; 469 clocks = <&rcc I2C3_K>; 470 resets = <&rcc I2C3_R>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 st,syscfg-fmp = <&syscfg 0x4 0x4>; 474 i2c-analog-filter; 475 status = "disabled"; 476 }; 477 478 i2c4: i2c@4c005000 { 479 compatible = "st,stm32mp13-i2c"; 480 reg = <0x4c005000 0x400>; 481 clocks = <&rcc I2C4_K>; 482 resets = <&rcc I2C4_R>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 st,syscfg-fmp = <&syscfg 0x4 0x8>; 486 i2c-analog-filter; 487 status = "disabled"; 488 }; 489 490 i2c5: i2c@4c006000 { 491 compatible = "st,stm32mp13-i2c"; 492 reg = <0x4c006000 0x400>; 493 clocks = <&rcc I2C5_K>; 494 resets = <&rcc I2C5_R>; 495 #address-cells = <1>; 496 #size-cells = <0>; 497 st,syscfg-fmp = <&syscfg 0x4 0x10>; 498 i2c-analog-filter; 499 status = "disabled"; 500 }; 501 502 timers12: timer@4c007000 { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 compatible = "st,stm32-timers"; 506 reg = <0x4c007000 0x400>; 507 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&rcc TIM12_K>; 509 clock-names = "int"; 510 511 counter { 512 compatible = "st,stm32-timer-counter"; 513 status = "disabled"; 514 }; 515 }; 516 517 timers13: timer@4c008000 { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 compatible = "st,stm32-timers"; 521 reg = <0x4c008000 0x400>; 522 clocks = <&rcc TIM13_K>; 523 clock-names = "int"; 524 status = "disabled"; 525 }; 526 527 timers14: timer@4c009000 { 528 #address-cells = <1>; 529 #size-cells = <0>; 530 compatible = "st,stm32-timers"; 531 reg = <0x4c009000 0x400>; 532 clocks = <&rcc TIM14_K>; 533 clock-names = "int"; 534 status = "disabled"; 535 }; 536 537 timers15: timer@4c00a000 { 538 #address-cells = <1>; 539 #size-cells = <0>; 540 compatible = "st,stm32-timers"; 541 reg = <0x4c00a000 0x400>; 542 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&rcc TIM15_K>; 544 clock-names = "int"; 545 status = "disabled"; 546 547 counter { 548 compatible = "st,stm32-timer-counter"; 549 status = "disabled"; 550 }; 551 }; 552 553 timers16: timer@4c00b000 { 554 #address-cells = <1>; 555 #size-cells = <0>; 556 compatible = "st,stm32-timers"; 557 reg = <0x4c00b000 0x400>; 558 clocks = <&rcc TIM16_K>; 559 clock-names = "int"; 560 status = "disabled"; 561 562 }; 563 564 timers17: timer@4c00c000 { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 compatible = "st,stm32-timers"; 568 reg = <0x4c00c000 0x400>; 569 clocks = <&rcc TIM17_K>; 570 clock-names = "int"; 571 status = "disabled"; 572 }; 573 574 lptimer2: timer@50021000 { 575 #address-cells = <1>; 576 #size-cells = <0>; 577 compatible = "st,stm32-lptimer"; 578 reg = <0x50021000 0x400>; 579 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&rcc LPTIM2_K>; 581 clock-names = "mux"; 582 status = "disabled"; 583 }; 584 585 lptimer3: timer@50022000 { 586 #address-cells = <1>; 587 #size-cells = <0>; 588 compatible = "st,stm32-lptimer"; 589 reg = <0x50022000 0x400>; 590 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&rcc LPTIM3_K>; 592 clock-names = "mux"; 593 status = "disabled"; 594 595 counter { 596 compatible = "st,stm32-lptimer-counter"; 597 status = "disabled"; 598 }; 599 }; 600 601 vrefbuf: vrefbuf@50025000 { 602 compatible = "st,stm32mp13-vrefbuf"; 603 reg = <0x50025000 0x8>; 604 regulator-name = "vrefbuf"; 605 regulator-min-microvolt = <1650000>; 606 regulator-max-microvolt = <2500000>; 607 clocks = <&rcc VREF>; 608 status = "disabled"; 609 }; 610 611 hash: hash@54003000 { 612 compatible = "st,stm32mp13-hash"; 613 reg = <0x54003000 0x400>; 614 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&rcc HASH1>; 616 resets = <&rcc HASH1_R>; 617 status = "disabled"; 618 }; 619 620 rng: rng@54004000 { 621 compatible = "st,stm32mp13-rng"; 622 reg = <0x54004000 0x400>; 623 clocks = <&rcc RNG1_K>; 624 resets = <&rcc RNG1_R>; 625 status = "disabled"; 626 }; 627 628 iwdg1: watchdog@5c003000 { 629 compatible = "st,stm32mp1-iwdg"; 630 reg = <0x5C003000 0x400>; 631 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 633 clock-names = "pclk", "lsi"; 634 status = "disabled"; 635 }; 636 637 stgen: stgen@5c008000 { 638 compatible = "st,stm32-stgen"; 639 reg = <0x5C008000 0x1000>; 640 }; 641 }; 642 }; 643}; 644