1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 11#include <dt-bindings/reset/stm32mp13-resets.h> 12 13/ { 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a7"; 23 device_type = "cpu"; 24 reg = <0>; 25 }; 26 }; 27 28 hse_monitor: hse-monitor { 29 compatible = "st,freq-monitor"; 30 counter = <&lptimer3 1 1 0 0>; 31 status = "disabled"; 32 }; 33 34 intc: interrupt-controller@a0021000 { 35 compatible = "arm,cortex-a7-gic"; 36 #interrupt-cells = <3>; 37 interrupt-controller; 38 reg = <0xa0021000 0x1000>, 39 <0xa0022000 0x2000>; 40 }; 41 42 psci { 43 compatible = "arm,psci-1.0"; 44 method = "smc"; 45 }; 46 47 clocks { 48 clk_hse: clk-hse { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <24000000>; 52 }; 53 54 clk_hsi: clk-hsi { 55 #clock-cells = <0>; 56 compatible = "fixed-clock"; 57 clock-frequency = <64000000>; 58 }; 59 60 clk_lse: clk-lse { 61 #clock-cells = <0>; 62 compatible = "fixed-clock"; 63 clock-frequency = <32768>; 64 }; 65 66 clk_lsi: clk-lsi { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 }; 71 72 clk_csi: clk-csi { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <4000000>; 76 }; 77 78 clk_i2sin: clk-i2sin { 79 #clock-cells = <0>; 80 compatible = "fixed-clock"; 81 clock-frequency = <19000000>; 82 }; 83 84 }; 85 86 soc { 87 compatible = "simple-bus"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 interrupt-parent = <&intc>; 91 ranges; 92 93 usart3: serial@4000f000 { 94 compatible = "st,stm32h7-uart"; 95 reg = <0x4000f000 0x400>; 96 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&rcc USART3_K>; 98 resets = <&rcc USART3_R>; 99 status = "disabled"; 100 }; 101 102 uart4: serial@40010000 { 103 compatible = "st,stm32h7-uart"; 104 reg = <0x40010000 0x400>; 105 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 106 clocks = <&rcc UART4_K>; 107 resets = <&rcc UART4_R>; 108 status = "disabled"; 109 }; 110 111 uart5: serial@40011000 { 112 compatible = "st,stm32h7-uart"; 113 reg = <0x40011000 0x400>; 114 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&rcc UART5_K>; 116 resets = <&rcc UART5_R>; 117 status = "disabled"; 118 }; 119 120 uart7: serial@40018000 { 121 compatible = "st,stm32h7-uart"; 122 reg = <0x40018000 0x400>; 123 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&rcc UART7_K>; 125 resets = <&rcc UART7_R>; 126 status = "disabled"; 127 }; 128 129 uart8: serial@40019000 { 130 compatible = "st,stm32h7-uart"; 131 reg = <0x40019000 0x400>; 132 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 133 clocks = <&rcc UART8_K>; 134 resets = <&rcc UART8_R>; 135 status = "disabled"; 136 }; 137 138 usart6: serial@44003000 { 139 compatible = "st,stm32h7-uart"; 140 reg = <0x44003000 0x400>; 141 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&rcc USART6_K>; 143 resets = <&rcc USART6_R>; 144 status = "disabled"; 145 }; 146 147 rcc: rcc@50000000 { 148 compatible = "st,stm32mp13-rcc", "syscon"; 149 reg = <0x50000000 0x1000>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 #clock-cells = <1>; 153 #reset-cells = <1>; 154 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 155 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 156 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 157 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 158 secure-interrupt-names = "wakeup"; 159 }; 160 161 pwr_regulators: pwr@50001000 { 162 compatible = "st,stm32mp1,pwr-reg"; 163 reg = <0x50001000 0x10>; 164 165 reg11: reg11 { 166 regulator-name = "reg11"; 167 regulator-min-microvolt = <1100000>; 168 regulator-max-microvolt = <1100000>; 169 }; 170 171 reg18: reg18 { 172 regulator-name = "reg18"; 173 regulator-min-microvolt = <1800000>; 174 regulator-max-microvolt = <1800000>; 175 }; 176 177 usb33: usb33 { 178 regulator-name = "usb33"; 179 regulator-min-microvolt = <3300000>; 180 regulator-max-microvolt = <3300000>; 181 }; 182 }; 183 184 pwr_irq: pwr@50001010 { 185 compatible = "st,stm32mp1,pwr-irq"; 186 status = "disabled"; 187 }; 188 189 syscfg: syscon@50020000 { 190 compatible = "st,stm32mp157-syscfg", "syscon"; 191 reg = <0x50020000 0x400>; 192 }; 193 194 iwdg2: watchdog@5a002000 { 195 compatible = "st,stm32mp1-iwdg"; 196 reg = <0x5a002000 0x400>; 197 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 199 clock-names = "pclk", "lsi"; 200 status = "disabled"; 201 }; 202 203 rtc: rtc@5c004000 { 204 compatible = "st,stm32mp13-rtc"; 205 reg = <0x5c004000 0x400>; 206 clocks = <&rcc RTCAPB>, <&rcc RTC>; 207 clock-names = "pclk", "rtc_ck"; 208 status = "disabled"; 209 }; 210 211 bsec: efuse@5c005000 { 212 compatible = "st,stm32mp13-bsec"; 213 reg = <0x5c005000 0x400>; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 217 cfg0_otp: cfg0_otp@0 { 218 reg = <0x0 0x2>; 219 }; 220 part_number_otp: part_number_otp@4 { 221 reg = <0x4 0x2>; 222 bits = <0 12>; 223 }; 224 monotonic_otp: monotonic_otp@10 { 225 reg = <0x10 0x4>; 226 }; 227 nand_otp: cfg9_otp@24 { 228 reg = <0x24 0x4>; 229 }; 230 uid_otp: uid_otp@34 { 231 reg = <0x34 0xc>; 232 }; 233 hw2_otp: hw2_otp@48 { 234 reg = <0x48 0x4>; 235 }; 236 ts_cal1: calib@5c { 237 reg = <0x5c 0x2>; 238 }; 239 ts_cal2: calib@5e { 240 reg = <0x5e 0x2>; 241 }; 242 pkh_otp: pkh_otp@60 { 243 reg = <0x60 0x20>; 244 }; 245 ethernet_mac1_address: mac1@e4 { 246 reg = <0xe4 0xc>; 247 st,non-secure-otp; 248 }; 249 oem_enc_key: oem_enc_key@170 { 250 reg = <0x170 0x10>; 251 }; 252 }; 253 254 tzc400: tzc@5c006000 { 255 compatible = "st,stm32mp1-tzc"; 256 reg = <0x5c006000 0x1000>; 257 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 258 st,mem-map = <0xc0000000 0x40000000>; 259 clocks = <&rcc TZC>; 260 }; 261 262 tamp: tamp@5c00a000 { 263 compatible = "st,stm32mp13-tamp"; 264 reg = <0x5c00a000 0x400>; 265 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&rcc RTCAPB>; 267 }; 268 269 pinctrl: pin-controller@50002000 { 270 #address-cells = <1>; 271 #size-cells = <1>; 272 compatible = "st,stm32mp135-pinctrl"; 273 ranges = <0 0x50002000 0x8400>; 274 pins-are-numbered; 275 276 gpioa: gpio@50002000 { 277 gpio-controller; 278 #gpio-cells = <2>; 279 interrupt-controller; 280 #interrupt-cells = <2>; 281 clocks = <&rcc GPIOA>; 282 reg = <0x0 0x400>; 283 st,bank-name = "GPIOA"; 284 ngpios = <16>; 285 gpio-ranges = <&pinctrl 0 0 16>; 286 }; 287 288 gpiob: gpio@50003000 { 289 gpio-controller; 290 #gpio-cells = <2>; 291 interrupt-controller; 292 #interrupt-cells = <2>; 293 clocks = <&rcc GPIOB>; 294 reg = <0x1000 0x400>; 295 st,bank-name = "GPIOB"; 296 ngpios = <16>; 297 gpio-ranges = <&pinctrl 0 16 16>; 298 }; 299 300 gpioc: gpio@50004000 { 301 gpio-controller; 302 #gpio-cells = <2>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 clocks = <&rcc GPIOC>; 306 reg = <0x2000 0x400>; 307 st,bank-name = "GPIOC"; 308 ngpios = <16>; 309 gpio-ranges = <&pinctrl 0 32 16>; 310 }; 311 312 gpiod: gpio@50005000 { 313 gpio-controller; 314 #gpio-cells = <2>; 315 interrupt-controller; 316 #interrupt-cells = <2>; 317 clocks = <&rcc GPIOD>; 318 reg = <0x3000 0x400>; 319 st,bank-name = "GPIOD"; 320 ngpios = <16>; 321 gpio-ranges = <&pinctrl 0 48 16>; 322 }; 323 324 gpioe: gpio@50006000 { 325 gpio-controller; 326 #gpio-cells = <2>; 327 interrupt-controller; 328 #interrupt-cells = <2>; 329 clocks = <&rcc GPIOE>; 330 reg = <0x4000 0x400>; 331 st,bank-name = "GPIOE"; 332 ngpios = <16>; 333 gpio-ranges = <&pinctrl 0 64 16>; 334 }; 335 336 gpiof: gpio@50007000 { 337 gpio-controller; 338 #gpio-cells = <2>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 clocks = <&rcc GPIOF>; 342 reg = <0x5000 0x400>; 343 st,bank-name = "GPIOF"; 344 ngpios = <16>; 345 gpio-ranges = <&pinctrl 0 80 16>; 346 }; 347 348 gpiog: gpio@50008000 { 349 gpio-controller; 350 #gpio-cells = <2>; 351 interrupt-controller; 352 #interrupt-cells = <2>; 353 clocks = <&rcc GPIOG>; 354 reg = <0x6000 0x400>; 355 st,bank-name = "GPIOG"; 356 ngpios = <16>; 357 gpio-ranges = <&pinctrl 0 96 16>; 358 }; 359 360 gpioh: gpio@50009000 { 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 clocks = <&rcc GPIOH>; 366 reg = <0x7000 0x400>; 367 st,bank-name = "GPIOH"; 368 ngpios = <15>; 369 gpio-ranges = <&pinctrl 0 112 15>; 370 }; 371 372 gpioi: gpio@5000a000 { 373 gpio-controller; 374 #gpio-cells = <2>; 375 interrupt-controller; 376 #interrupt-cells = <2>; 377 clocks = <&rcc GPIOI>; 378 reg = <0x8000 0x400>; 379 st,bank-name = "GPIOI"; 380 ngpios = <8>; 381 gpio-ranges = <&pinctrl 0 128 8>; 382 }; 383 }; 384 385 etzpc: etzpc@5c007000 { 386 compatible = "st,stm32-etzpc", "firewall-bus"; 387 reg = <0x5C007000 0x400>; 388 clocks = <&rcc TZPC>; 389 #address-cells = <1>; 390 #size-cells = <1>; 391 392 adc_2: adc@48004000 { 393 reg = <0x48004000 0x400>; 394 compatible = "st,stm32mp13-adc-core"; 395 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 397 clock-names = "bus", "adc"; 398 interrupt-controller; 399 #interrupt-cells = <1>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 status = "disabled"; 403 404 adc2: adc@0 { 405 compatible = "st,stm32mp13-adc"; 406 reg = <0x0>; 407 #io-channel-cells = <1>; 408 #address-cells = <1>; 409 #size-cells = <0>; 410 interrupt-parent = <&adc_2>; 411 interrupts = <0>; 412 status = "disabled"; 413 414 channel@13 { 415 reg = <13>; 416 label = "vrefint"; 417 }; 418 419 channel@14 { 420 reg = <14>; 421 label = "vddcore"; 422 }; 423 424 channel@16 { 425 reg = <16>; 426 label = "vddcpu"; 427 }; 428 429 channel@17 { 430 reg = <17>; 431 label = "vddq_ddr"; 432 }; 433 }; 434 }; 435 436 usart1: serial@4c000000 { 437 compatible = "st,stm32h7-uart"; 438 reg = <0x4c000000 0x400>; 439 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&rcc USART1_K>; 441 resets = <&rcc USART1_R>; 442 status = "disabled"; 443 }; 444 445 usart2: serial@4c001000 { 446 compatible = "st,stm32h7-uart"; 447 reg = <0x4c001000 0x400>; 448 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&rcc USART2_K>; 450 resets = <&rcc USART2_R>; 451 status = "disabled"; 452 }; 453 454 i2c3: i2c@4c004000 { 455 compatible = "st,stm32mp13-i2c"; 456 reg = <0x4c004000 0x400>; 457 clocks = <&rcc I2C3_K>; 458 resets = <&rcc I2C3_R>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 st,syscfg-fmp = <&syscfg 0x4 0x4>; 462 i2c-analog-filter; 463 status = "disabled"; 464 }; 465 466 i2c4: i2c@4c005000 { 467 compatible = "st,stm32mp13-i2c"; 468 reg = <0x4c005000 0x400>; 469 clocks = <&rcc I2C4_K>; 470 resets = <&rcc I2C4_R>; 471 #address-cells = <1>; 472 #size-cells = <0>; 473 st,syscfg-fmp = <&syscfg 0x4 0x8>; 474 i2c-analog-filter; 475 status = "disabled"; 476 }; 477 478 i2c5: i2c@4c006000 { 479 compatible = "st,stm32mp13-i2c"; 480 reg = <0x4c006000 0x400>; 481 clocks = <&rcc I2C5_K>; 482 resets = <&rcc I2C5_R>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 st,syscfg-fmp = <&syscfg 0x4 0x10>; 486 i2c-analog-filter; 487 status = "disabled"; 488 }; 489 490 timers12: timer@4c007000 { 491 #address-cells = <1>; 492 #size-cells = <0>; 493 compatible = "st,stm32-timers"; 494 reg = <0x4c007000 0x400>; 495 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&rcc TIM12_K>; 497 clock-names = "int"; 498 499 counter { 500 compatible = "st,stm32-timer-counter"; 501 status = "disabled"; 502 }; 503 }; 504 505 timers13: timer@4c008000 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 compatible = "st,stm32-timers"; 509 reg = <0x4c008000 0x400>; 510 clocks = <&rcc TIM13_K>; 511 clock-names = "int"; 512 status = "disabled"; 513 }; 514 515 timers14: timer@4c009000 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 compatible = "st,stm32-timers"; 519 reg = <0x4c009000 0x400>; 520 clocks = <&rcc TIM14_K>; 521 clock-names = "int"; 522 status = "disabled"; 523 }; 524 525 timers15: timer@4c00a000 { 526 #address-cells = <1>; 527 #size-cells = <0>; 528 compatible = "st,stm32-timers"; 529 reg = <0x4c00a000 0x400>; 530 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 531 clocks = <&rcc TIM15_K>; 532 clock-names = "int"; 533 status = "disabled"; 534 535 counter { 536 compatible = "st,stm32-timer-counter"; 537 status = "disabled"; 538 }; 539 }; 540 541 timers16: timer@4c00b000 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 compatible = "st,stm32-timers"; 545 reg = <0x4c00b000 0x400>; 546 clocks = <&rcc TIM16_K>; 547 clock-names = "int"; 548 status = "disabled"; 549 550 }; 551 552 timers17: timer@4c00c000 { 553 #address-cells = <1>; 554 #size-cells = <0>; 555 compatible = "st,stm32-timers"; 556 reg = <0x4c00c000 0x400>; 557 clocks = <&rcc TIM17_K>; 558 clock-names = "int"; 559 status = "disabled"; 560 }; 561 562 lptimer2: timer@50021000 { 563 #address-cells = <1>; 564 #size-cells = <0>; 565 compatible = "st,stm32-lptimer"; 566 reg = <0x50021000 0x400>; 567 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 568 clocks = <&rcc LPTIM2_K>; 569 clock-names = "mux"; 570 status = "disabled"; 571 }; 572 573 lptimer3: timer@50022000 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 compatible = "st,stm32-lptimer"; 577 reg = <0x50022000 0x400>; 578 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&rcc LPTIM3_K>; 580 clock-names = "mux"; 581 status = "disabled"; 582 583 counter { 584 compatible = "st,stm32-lptimer-counter"; 585 status = "disabled"; 586 }; 587 }; 588 589 vrefbuf: vrefbuf@50025000 { 590 compatible = "st,stm32mp13-vrefbuf"; 591 reg = <0x50025000 0x8>; 592 regulator-name = "vrefbuf"; 593 regulator-min-microvolt = <1650000>; 594 regulator-max-microvolt = <2500000>; 595 clocks = <&rcc VREF>; 596 status = "disabled"; 597 }; 598 599 hash: hash@54003000 { 600 compatible = "st,stm32mp13-hash"; 601 reg = <0x54003000 0x400>; 602 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&rcc HASH1>; 604 resets = <&rcc HASH1_R>; 605 status = "disabled"; 606 }; 607 608 rng: rng@54004000 { 609 compatible = "st,stm32mp13-rng"; 610 reg = <0x54004000 0x400>; 611 clocks = <&rcc RNG1_K>; 612 resets = <&rcc RNG1_R>; 613 status = "disabled"; 614 }; 615 616 iwdg1: watchdog@5c003000 { 617 compatible = "st,stm32mp1-iwdg"; 618 reg = <0x5C003000 0x400>; 619 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 621 clock-names = "pclk", "lsi"; 622 status = "disabled"; 623 }; 624 625 stgen: stgen@5c008000 { 626 compatible = "st,stm32-stgen"; 627 reg = <0x5C008000 0x1000>; 628 }; 629 }; 630 }; 631}; 632