1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2021-2025 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6 7#include <dt-bindings/clock/stm32mp13-clks.h> 8#include <dt-bindings/clock/stm32mp13-clksrc.h> 9#include <dt-bindings/firewall/stm32mp13-etzpc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/regulator/st,stm32mp13-regulator.h> 12#include <dt-bindings/reset/stm32mp13-resets.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 compatible = "arm,cortex-a7"; 24 device_type = "cpu"; 25 reg = <0>; 26 clocks = <&rcc CK_MPU>; 27 clock-names = "cpu"; 28 operating-points-v2 = <&cpu0_opp_table>; 29 nvmem-cells = <&part_number_otp>; 30 nvmem-cell-names = "part_number"; 31 }; 32 }; 33 34 cpu0_opp_table: cpu0-opp-table { 35 compatible = "operating-points-v2"; 36 37 /* Non‑overdrive OPP mission profile */ 38 opp-650000000 { 39 opp-hz = /bits/ 64 <650000000>; 40 opp-microvolt = <1250000>; 41 opp-supported-hw = <0x3>; 42 st,opp-default; 43 }; 44 45 /* Overdrive OPP: 10‑year life activity @100% activity rate */ 46 opp-900000000 { 47 opp-hz = /bits/ 64 <900000000>; 48 opp-microvolt = <1350000>; 49 opp-supported-hw = <0x2>; 50 st,opp-default; 51 }; 52 53 /* Overdrive OPP: 10‑year life activity @25% activity rate */ 54 opp-1000000000 { 55 opp-hz = /bits/ 64 <1000000000>; 56 opp-microvolt = <1350000>; 57 opp-supported-hw = <0x2>; 58 }; 59 }; 60 61 hse_monitor: hse-monitor { 62 compatible = "st,freq-monitor"; 63 counter = <&lptimer3 1 1 0 0>; 64 status = "disabled"; 65 }; 66 67 intc: interrupt-controller@a0021000 { 68 compatible = "arm,cortex-a7-gic"; 69 #interrupt-cells = <3>; 70 interrupt-controller; 71 reg = <0xa0021000 0x1000>, 72 <0xa0022000 0x2000>; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0"; 77 method = "smc"; 78 }; 79 80 clocks { 81 clk_hse: clk-hse { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <24000000>; 85 }; 86 87 clk_hsi: clk-hsi { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <64000000>; 91 }; 92 93 clk_lse: clk-lse { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <32768>; 97 }; 98 99 clk_lsi: clk-lsi { 100 #clock-cells = <0>; 101 compatible = "fixed-clock"; 102 clock-frequency = <32000>; 103 }; 104 105 clk_csi: clk-csi { 106 #clock-cells = <0>; 107 compatible = "fixed-clock"; 108 clock-frequency = <4000000>; 109 }; 110 111 clk_i2sin: clk-i2sin { 112 #clock-cells = <0>; 113 compatible = "fixed-clock"; 114 clock-frequency = <19000000>; 115 }; 116 117 }; 118 119 sdmmc1_io: sdmmc1_io { 120 compatible = "st,stm32mp13-iod"; 121 regulator-name = "sdmmc1_io"; 122 regulator-always-on; 123 }; 124 125 sdmmc2_io: sdmmc2_io { 126 compatible = "st,stm32mp13-iod"; 127 regulator-name = "sdmmc2_io"; 128 regulator-always-on; 129 }; 130 131 soc { 132 compatible = "simple-bus"; 133 #address-cells = <1>; 134 #size-cells = <1>; 135 interrupt-parent = <&intc>; 136 ranges; 137 138 usart3: serial@4000f000 { 139 compatible = "st,stm32h7-uart"; 140 reg = <0x4000f000 0x400>; 141 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&rcc USART3_K>; 143 resets = <&rcc USART3_R>; 144 status = "disabled"; 145 }; 146 147 uart4: serial@40010000 { 148 compatible = "st,stm32h7-uart"; 149 reg = <0x40010000 0x400>; 150 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 151 clocks = <&rcc UART4_K>; 152 resets = <&rcc UART4_R>; 153 status = "disabled"; 154 }; 155 156 uart5: serial@40011000 { 157 compatible = "st,stm32h7-uart"; 158 reg = <0x40011000 0x400>; 159 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&rcc UART5_K>; 161 resets = <&rcc UART5_R>; 162 status = "disabled"; 163 }; 164 165 i2c1: i2c@40012000 { 166 compatible = "st,stm32mp13-i2c"; 167 reg = <0x40012000 0x400>; 168 clocks = <&rcc I2C1_K>; 169 resets = <&rcc I2C1_R>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 st,syscfg-fmp = <&syscfg 0x4 0x1>; 173 i2c-analog-filter; 174 status = "disabled"; 175 }; 176 177 i2c2: i2c@40013000 { 178 compatible = "st,stm32mp13-i2c"; 179 reg = <0x40013000 0x400>; 180 clocks = <&rcc I2C2_K>; 181 resets = <&rcc I2C2_R>; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 st,syscfg-fmp = <&syscfg 0x4 0x2>; 185 i2c-analog-filter; 186 status = "disabled"; 187 }; 188 189 uart7: serial@40018000 { 190 compatible = "st,stm32h7-uart"; 191 reg = <0x40018000 0x400>; 192 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 193 clocks = <&rcc UART7_K>; 194 resets = <&rcc UART7_R>; 195 status = "disabled"; 196 }; 197 198 uart8: serial@40019000 { 199 compatible = "st,stm32h7-uart"; 200 reg = <0x40019000 0x400>; 201 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&rcc UART8_K>; 203 resets = <&rcc UART8_R>; 204 status = "disabled"; 205 }; 206 207 usart6: serial@44003000 { 208 compatible = "st,stm32h7-uart"; 209 reg = <0x44003000 0x400>; 210 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&rcc USART6_K>; 212 resets = <&rcc USART6_R>; 213 status = "disabled"; 214 }; 215 216 rcc: rcc@50000000 { 217 compatible = "st,stm32mp13-rcc", "syscon"; 218 reg = <0x50000000 0x1000>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 #clock-cells = <1>; 222 #reset-cells = <1>; 223 clocks = <&clk_hse>, <&clk_hsi>, <&clk_lse>, <&clk_lsi>, <&clk_csi>, <&clk_i2sin>; 224 clock-names = "clk-hse", "clk-hsi", "clk-lse", "clk-lsi", "clk-csi", "clk-i2sin"; 225 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 226 secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 227 secure-interrupt-names = "wakeup"; 228 }; 229 230 pwr_regulators: pwr@50001000 { 231 compatible = "st,stm32mp1-pwr-reg"; 232 reg = <0x50001000 0x10>; 233 234 reg11: reg11 { 235 regulator-name = "reg11"; 236 regulator-min-microvolt = <1100000>; 237 regulator-max-microvolt = <1100000>; 238 }; 239 240 reg18: reg18 { 241 regulator-name = "reg18"; 242 regulator-min-microvolt = <1800000>; 243 regulator-max-microvolt = <1800000>; 244 }; 245 246 usb33: usb33 { 247 regulator-name = "usb33"; 248 regulator-min-microvolt = <3300000>; 249 regulator-max-microvolt = <3300000>; 250 }; 251 }; 252 253 pwr_irq: pwr@50001010 { 254 compatible = "st,stm32mp1,pwr-irq"; 255 status = "disabled"; 256 }; 257 258 exti: interrupt-controller@5000d000 { 259 compatible = "st,stm32mp1-exti"; 260 interrupt-controller; 261 #interrupt-cells = <2>; 262 reg = <0x5000d000 0x400>; 263 interrupts-extended = 264 <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ 265 <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 266 <&intc GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 267 <&intc GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 268 <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 269 <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 270 <&intc GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 271 <&intc GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 272 <&intc GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 273 <&intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 274 <&intc GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ 275 <&intc GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 276 <&intc GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 277 <&intc GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 278 <&intc GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 279 <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 280 <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 281 <0>, 282 <&intc GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 283 <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 284 <0>, /* EXTI_20 */ 285 <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 286 <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 287 <&intc GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 288 <&intc GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 289 <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 290 <&intc GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 291 <&intc GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 292 <&intc GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 293 <&intc GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 294 <&intc GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ 295 <&intc GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 296 <&intc GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 297 <&intc GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 298 <0>, 299 <0>, 300 <0>, 301 <0>, 302 <0>, 303 <0>, 304 <0>, /* EXTI_40 */ 305 <0>, 306 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 307 <&intc GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 308 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 309 <0>, 310 <0>, 311 <&intc GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 312 <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 313 <0>, 314 <&intc GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ 315 <0>, 316 <&intc GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 317 <&intc GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 318 <0>, 319 <0>, 320 <0>, 321 <0>, 322 <0>, 323 <0>, 324 <0>, /* EXTI_60 */ 325 <0>, 326 <0>, 327 <0>, 328 <0>, 329 <0>, 330 <0>, 331 <0>, 332 <&intc GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 333 <0>, 334 <&intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ 335 }; 336 337 syscfg: syscon@50020000 { 338 compatible = "st,stm32mp157-syscfg", "syscon"; 339 reg = <0x50020000 0x400>; 340 }; 341 342 iwdg2: watchdog@5a002000 { 343 compatible = "st,stm32mp1-iwdg"; 344 reg = <0x5a002000 0x400>; 345 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&rcc IWDG2>, <&rcc CK_LSI>; 347 clock-names = "pclk", "lsi"; 348 status = "disabled"; 349 }; 350 351 rtc: rtc@5c004000 { 352 compatible = "st,stm32mp13-rtc"; 353 reg = <0x5c004000 0x400>; 354 clocks = <&rcc RTCAPB>, <&rcc RTC>; 355 clock-names = "pclk", "rtc_ck"; 356 }; 357 358 bsec: efuse@5c005000 { 359 compatible = "st,stm32mp13-bsec"; 360 reg = <0x5c005000 0x400>; 361 #address-cells = <1>; 362 #size-cells = <1>; 363 364 cfg0_otp: cfg0_otp@0 { 365 reg = <0x0 0x2>; 366 }; 367 part_number_otp: part_number_otp@4 { 368 reg = <0x4 0x2>; 369 bits = <0 12>; 370 }; 371 monotonic_otp: monotonic_otp@10 { 372 reg = <0x10 0x4>; 373 }; 374 nand_otp: cfg9_otp@24 { 375 reg = <0x24 0x4>; 376 }; 377 uid_otp: uid_otp@34 { 378 reg = <0x34 0xc>; 379 }; 380 hw2_otp: hw2_otp@48 { 381 reg = <0x48 0x4>; 382 }; 383 ts_cal1: calib@5c { 384 reg = <0x5c 0x2>; 385 }; 386 ts_cal2: calib@5e { 387 reg = <0x5e 0x2>; 388 }; 389 pkh_otp: pkh_otp@60 { 390 reg = <0x60 0x20>; 391 }; 392 ethernet_mac1_address: mac1@e4 { 393 reg = <0xe4 0xc>; 394 st,non-secure-otp; 395 }; 396 oem_enc_key: oem_enc_key@170 { 397 reg = <0x170 0x10>; 398 }; 399 }; 400 401 tzc400: tzc@5c006000 { 402 compatible = "st,stm32mp1-tzc"; 403 reg = <0x5c006000 0x1000>; 404 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 405 st,mem-map = <0xc0000000 0x40000000>; 406 clocks = <&rcc TZC>; 407 }; 408 409 tamp: tamp@5c00a000 { 410 compatible = "st,stm32mp13-tamp"; 411 reg = <0x5c00a000 0x400>; 412 interrupts-extended = <&exti 18 IRQ_TYPE_EDGE_RISING>; 413 clocks = <&rcc RTCAPB>; 414 st,backup-zones = <10 5 17>; 415 }; 416 417 pinctrl: pin-controller@50002000 { 418 #address-cells = <1>; 419 #size-cells = <1>; 420 compatible = "st,stm32mp135-pinctrl"; 421 ranges = <0 0x50002000 0x8400>; 422 423 gpioa: gpio@50002000 { 424 gpio-controller; 425 #gpio-cells = <2>; 426 interrupt-controller; 427 #interrupt-cells = <2>; 428 #access-controller-cells = <1>; 429 clocks = <&rcc GPIOA>; 430 reg = <0x0 0x400>; 431 st,bank-name = "GPIOA"; 432 ngpios = <16>; 433 gpio-ranges = <&pinctrl 0 0 16>; 434 }; 435 436 gpiob: gpio@50003000 { 437 gpio-controller; 438 #gpio-cells = <2>; 439 interrupt-controller; 440 #interrupt-cells = <2>; 441 #access-controller-cells = <1>; 442 clocks = <&rcc GPIOB>; 443 reg = <0x1000 0x400>; 444 st,bank-name = "GPIOB"; 445 ngpios = <16>; 446 gpio-ranges = <&pinctrl 0 16 16>; 447 }; 448 449 gpioc: gpio@50004000 { 450 gpio-controller; 451 #gpio-cells = <2>; 452 interrupt-controller; 453 #interrupt-cells = <2>; 454 #access-controller-cells = <1>; 455 clocks = <&rcc GPIOC>; 456 reg = <0x2000 0x400>; 457 st,bank-name = "GPIOC"; 458 ngpios = <16>; 459 gpio-ranges = <&pinctrl 0 32 16>; 460 }; 461 462 gpiod: gpio@50005000 { 463 gpio-controller; 464 #gpio-cells = <2>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 #access-controller-cells = <1>; 468 clocks = <&rcc GPIOD>; 469 reg = <0x3000 0x400>; 470 st,bank-name = "GPIOD"; 471 ngpios = <16>; 472 gpio-ranges = <&pinctrl 0 48 16>; 473 }; 474 475 gpioe: gpio@50006000 { 476 gpio-controller; 477 #gpio-cells = <2>; 478 interrupt-controller; 479 #interrupt-cells = <2>; 480 #access-controller-cells = <1>; 481 clocks = <&rcc GPIOE>; 482 reg = <0x4000 0x400>; 483 st,bank-name = "GPIOE"; 484 ngpios = <16>; 485 gpio-ranges = <&pinctrl 0 64 16>; 486 }; 487 488 gpiof: gpio@50007000 { 489 gpio-controller; 490 #gpio-cells = <2>; 491 interrupt-controller; 492 #interrupt-cells = <2>; 493 #access-controller-cells = <1>; 494 clocks = <&rcc GPIOF>; 495 reg = <0x5000 0x400>; 496 st,bank-name = "GPIOF"; 497 ngpios = <16>; 498 gpio-ranges = <&pinctrl 0 80 16>; 499 }; 500 501 gpiog: gpio@50008000 { 502 gpio-controller; 503 #gpio-cells = <2>; 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 #access-controller-cells = <1>; 507 clocks = <&rcc GPIOG>; 508 reg = <0x6000 0x400>; 509 st,bank-name = "GPIOG"; 510 ngpios = <16>; 511 gpio-ranges = <&pinctrl 0 96 16>; 512 }; 513 514 gpioh: gpio@50009000 { 515 gpio-controller; 516 #gpio-cells = <2>; 517 interrupt-controller; 518 #interrupt-cells = <2>; 519 #access-controller-cells = <1>; 520 clocks = <&rcc GPIOH>; 521 reg = <0x7000 0x400>; 522 st,bank-name = "GPIOH"; 523 ngpios = <15>; 524 gpio-ranges = <&pinctrl 0 112 15>; 525 }; 526 527 gpioi: gpio@5000a000 { 528 gpio-controller; 529 #gpio-cells = <2>; 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 #access-controller-cells = <1>; 533 clocks = <&rcc GPIOI>; 534 reg = <0x8000 0x400>; 535 st,bank-name = "GPIOI"; 536 ngpios = <8>; 537 gpio-ranges = <&pinctrl 0 128 8>; 538 }; 539 }; 540 541 etzpc: etzpc@5c007000 { 542 compatible = "st,stm32-etzpc", "simple-bus"; 543 reg = <0x5C007000 0x400>; 544 clocks = <&rcc TZPC>; 545 #address-cells = <1>; 546 #size-cells = <1>; 547 #access-controller-cells = <1>; 548 549 adc_2: adc@48004000 { 550 reg = <0x48004000 0x400>; 551 compatible = "st,stm32mp13-adc-core"; 552 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&rcc ADC2>, <&rcc ADC2_K>; 554 clock-names = "bus", "adc"; 555 interrupt-controller; 556 #interrupt-cells = <1>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 access-controllers = <&etzpc STM32MP1_ETZPC_ADC2_ID>; 560 status = "disabled"; 561 562 adc2: adc@0 { 563 compatible = "st,stm32mp13-adc"; 564 reg = <0x0>; 565 #io-channel-cells = <1>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 interrupt-parent = <&adc_2>; 569 interrupts = <0>; 570 status = "disabled"; 571 572 channel@13 { 573 reg = <13>; 574 label = "vrefint"; 575 }; 576 577 channel@14 { 578 reg = <14>; 579 label = "vddcore"; 580 }; 581 582 channel@16 { 583 reg = <16>; 584 label = "vddcpu"; 585 }; 586 587 channel@17 { 588 reg = <17>; 589 label = "vddq_ddr"; 590 }; 591 }; 592 }; 593 594 usart1: serial@4c000000 { 595 compatible = "st,stm32h7-uart"; 596 reg = <0x4c000000 0x400>; 597 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 598 clocks = <&rcc USART1_K>; 599 resets = <&rcc USART1_R>; 600 access-controllers = <&etzpc STM32MP1_ETZPC_USART1_ID>; 601 status = "disabled"; 602 }; 603 604 usart2: serial@4c001000 { 605 compatible = "st,stm32h7-uart"; 606 reg = <0x4c001000 0x400>; 607 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 608 clocks = <&rcc USART2_K>; 609 resets = <&rcc USART2_R>; 610 access-controllers = <&etzpc STM32MP1_ETZPC_USART2_ID>; 611 status = "disabled"; 612 }; 613 614 i2c3: i2c@4c004000 { 615 compatible = "st,stm32mp13-i2c"; 616 reg = <0x4c004000 0x400>; 617 clocks = <&rcc I2C3_K>; 618 resets = <&rcc I2C3_R>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 st,syscfg-fmp = <&syscfg 0x4 0x4>; 622 i2c-analog-filter; 623 access-controllers = <&etzpc STM32MP1_ETZPC_I2C3_ID>; 624 status = "disabled"; 625 }; 626 627 i2c4: i2c@4c005000 { 628 compatible = "st,stm32mp13-i2c"; 629 reg = <0x4c005000 0x400>; 630 clocks = <&rcc I2C4_K>; 631 resets = <&rcc I2C4_R>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 st,syscfg-fmp = <&syscfg 0x4 0x8>; 635 i2c-analog-filter; 636 access-controllers = <&etzpc STM32MP1_ETZPC_I2C4_ID>; 637 status = "disabled"; 638 }; 639 640 i2c5: i2c@4c006000 { 641 compatible = "st,stm32mp13-i2c"; 642 reg = <0x4c006000 0x400>; 643 clocks = <&rcc I2C5_K>; 644 resets = <&rcc I2C5_R>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 st,syscfg-fmp = <&syscfg 0x4 0x10>; 648 i2c-analog-filter; 649 access-controllers = <&etzpc STM32MP1_ETZPC_I2C5_ID>; 650 status = "disabled"; 651 }; 652 653 timers12: timer@4c007000 { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 compatible = "st,stm32-timers"; 657 reg = <0x4c007000 0x400>; 658 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&rcc TIM12_K>; 660 clock-names = "int"; 661 access-controllers = <&etzpc STM32MP1_ETZPC_TIM12_ID>; 662 status = "disabled"; 663 664 counter { 665 compatible = "st,stm32-timer-counter"; 666 status = "disabled"; 667 }; 668 }; 669 670 timers13: timer@4c008000 { 671 #address-cells = <1>; 672 #size-cells = <0>; 673 compatible = "st,stm32-timers"; 674 reg = <0x4c008000 0x400>; 675 clocks = <&rcc TIM13_K>; 676 clock-names = "int"; 677 access-controllers = <&etzpc STM32MP1_ETZPC_TIM13_ID>; 678 status = "disabled"; 679 }; 680 681 timers14: timer@4c009000 { 682 #address-cells = <1>; 683 #size-cells = <0>; 684 compatible = "st,stm32-timers"; 685 reg = <0x4c009000 0x400>; 686 clocks = <&rcc TIM14_K>; 687 clock-names = "int"; 688 access-controllers = <&etzpc STM32MP1_ETZPC_TIM14_ID>; 689 status = "disabled"; 690 }; 691 692 timers15: timer@4c00a000 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 compatible = "st,stm32-timers"; 696 reg = <0x4c00a000 0x400>; 697 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&rcc TIM15_K>; 699 clock-names = "int"; 700 access-controllers = <&etzpc STM32MP1_ETZPC_TIM15_ID>; 701 status = "disabled"; 702 703 counter { 704 compatible = "st,stm32-timer-counter"; 705 status = "disabled"; 706 }; 707 }; 708 709 timers16: timer@4c00b000 { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 compatible = "st,stm32-timers"; 713 reg = <0x4c00b000 0x400>; 714 clocks = <&rcc TIM16_K>; 715 clock-names = "int"; 716 access-controllers = <&etzpc STM32MP1_ETZPC_TIM16_ID>; 717 status = "disabled"; 718 }; 719 720 timers17: timer@4c00c000 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 compatible = "st,stm32-timers"; 724 reg = <0x4c00c000 0x400>; 725 clocks = <&rcc TIM17_K>; 726 clock-names = "int"; 727 access-controllers = <&etzpc STM32MP1_ETZPC_TIM17_ID>; 728 status = "disabled"; 729 }; 730 731 lptimer2: timer@50021000 { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 compatible = "st,stm32-lptimer"; 735 reg = <0x50021000 0x400>; 736 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 737 clocks = <&rcc LPTIM2_K>; 738 clock-names = "mux"; 739 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM2_ID>; 740 status = "disabled"; 741 }; 742 743 lptimer3: timer@50022000 { 744 #address-cells = <1>; 745 #size-cells = <0>; 746 compatible = "st,stm32-lptimer"; 747 reg = <0x50022000 0x400>; 748 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&rcc LPTIM3_K>; 750 clock-names = "mux"; 751 access-controllers = <&etzpc STM32MP1_ETZPC_LPTIM3_ID>; 752 status = "disabled"; 753 754 counter { 755 compatible = "st,stm32-lptimer-counter"; 756 status = "disabled"; 757 }; 758 }; 759 760 vrefbuf: vrefbuf@50025000 { 761 compatible = "st,stm32mp13-vrefbuf"; 762 reg = <0x50025000 0x8>; 763 regulator-name = "vrefbuf"; 764 regulator-min-microvolt = <1650000>; 765 regulator-max-microvolt = <2500000>; 766 clocks = <&rcc VREF>; 767 access-controllers = <&etzpc STM32MP1_ETZPC_VREFBUF_ID>; 768 status = "disabled"; 769 }; 770 771 hash: hash@54003000 { 772 compatible = "st,stm32mp13-hash"; 773 reg = <0x54003000 0x400>; 774 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&rcc HASH1>; 776 resets = <&rcc HASH1_R>; 777 access-controllers = <&etzpc STM32MP1_ETZPC_HASH_ID>; 778 status = "disabled"; 779 }; 780 781 rng: rng@54004000 { 782 compatible = "st,stm32mp13-rng"; 783 reg = <0x54004000 0x400>; 784 clocks = <&rcc RNG1_K>; 785 resets = <&rcc RNG1_R>; 786 access-controllers = <&etzpc STM32MP1_ETZPC_RNG_ID>; 787 status = "disabled"; 788 }; 789 790 iwdg1: watchdog@5c003000 { 791 compatible = "st,stm32mp1-iwdg"; 792 reg = <0x5C003000 0x400>; 793 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 794 clocks = <&rcc IWDG1>, <&rcc CK_LSI>; 795 clock-names = "pclk", "lsi"; 796 access-controllers = <&etzpc STM32MP1_ETZPC_IWDG1_ID>; 797 status = "disabled"; 798 }; 799 800 stgen: stgen@5c008000 { 801 compatible = "st,stm32-stgen"; 802 reg = <0x5C008000 0x1000>; 803 access-controllers = <&etzpc STM32MP1_ETZPC_STGENC_ID>; 804 }; 805 }; 806 }; 807}; 808