1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 }; 36 }; 37 38 pmu { 39 compatible = "arm,cortex-a5-pmu"; 40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 41 }; 42 43 etb@740000 { 44 compatible = "arm,coresight-etb10", "arm,primecell"; 45 reg = <0x740000 0x1000>; 46 47 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 48 clock-names = "apb_pclk"; 49 50 in-ports { 51 port { 52 etb_in: endpoint { 53 remote-endpoint = <&etm_out>; 54 }; 55 }; 56 }; 57 }; 58 59 etm@73c000 { 60 compatible = "arm,coresight-etm3x", "arm,primecell"; 61 reg = <0x73c000 0x1000>; 62 63 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 64 clock-names = "apb_pclk"; 65 66 out-ports { 67 port { 68 etm_out: endpoint { 69 remote-endpoint = <&etb_in>; 70 }; 71 }; 72 }; 73 }; 74 75 memory@20000000 { 76 device_type = "memory"; 77 reg = <0x20000000 0x20000000>; 78 }; 79 80 clocks { 81 slow_xtal: slow_xtal { 82 compatible = "fixed-clock"; 83 #clock-cells = <0>; 84 clock-frequency = <0>; 85 }; 86 87 main_xtal: main_xtal { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <0>; 91 }; 92 }; 93 94 ns_sram: sram@200000 { 95 compatible = "atmel,sama5d2-sram", "mmio-sram"; 96 reg = <0x00200000 0x20000>; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 ranges = <0 0x00200000 0x20000>; 100 status = "disabled"; 101 secure-status = "okay"; 102 }; 103 104 ahb { 105 compatible = "simple-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 nfc_sram: sram@100000 { 111 compatible = "mmio-sram"; 112 no-memory-wc; 113 reg = <0x00100000 0x2400>; 114 #address-cells = <1>; 115 #size-cells = <1>; 116 ranges = <0 0x00100000 0x2400>; 117 118 }; 119 120 usb0: gadget@300000 { 121 compatible = "atmel,sama5d3-udc"; 122 reg = <0x00300000 0x100000 123 0xfc02c000 0x400>; 124 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 125 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 126 clock-names = "pclk", "hclk"; 127 status = "disabled"; 128 }; 129 130 usb1: ohci@400000 { 131 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 132 reg = <0x00400000 0x100000>; 133 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 134 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 135 clock-names = "ohci_clk", "hclk", "uhpck"; 136 status = "disabled"; 137 }; 138 139 usb2: ehci@500000 { 140 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 141 reg = <0x00500000 0x100000>; 142 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 143 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 144 clock-names = "usb_clk", "ehci_clk"; 145 status = "disabled"; 146 }; 147 148 L2: cache-controller@a00000 { 149 compatible = "arm,pl310-cache"; 150 reg = <0x00a00000 0x1000>; 151 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 152 cache-unified; 153 cache-level = <2>; 154 }; 155 156 ebi: ebi@10000000 { 157 compatible = "atmel,sama5d3-ebi"; 158 #address-cells = <2>; 159 #size-cells = <1>; 160 atmel,smc = <&hsmc>; 161 reg = <0x10000000 0x10000000 162 0x60000000 0x30000000>; 163 ranges = <0x0 0x0 0x10000000 0x10000000 164 0x1 0x0 0x60000000 0x10000000 165 0x2 0x0 0x70000000 0x10000000 166 0x3 0x0 0x80000000 0x10000000>; 167 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 168 status = "disabled"; 169 170 nand_controller: nand-controller { 171 compatible = "atmel,sama5d3-nand-controller"; 172 atmel,nfc-sram = <&nfc_sram>; 173 atmel,nfc-io = <&nfc_io>; 174 ecc-engine = <&pmecc>; 175 #address-cells = <2>; 176 #size-cells = <1>; 177 ranges; 178 status = "disabled"; 179 }; 180 }; 181 182 sdmmc0: sdio-host@a0000000 { 183 compatible = "atmel,sama5d2-sdhci"; 184 reg = <0xa0000000 0x300>; 185 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 186 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 187 clock-names = "hclock", "multclk", "baseclk"; 188 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 189 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 190 assigned-clock-rates = <480000000>; 191 status = "disabled"; 192 }; 193 194 sdmmc1: sdio-host@b0000000 { 195 compatible = "atmel,sama5d2-sdhci"; 196 reg = <0xb0000000 0x300>; 197 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 198 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 199 clock-names = "hclock", "multclk", "baseclk"; 200 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 201 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 202 assigned-clock-rates = <480000000>; 203 status = "disabled"; 204 }; 205 206 nfc_io: nfc-io@c0000000 { 207 compatible = "atmel,sama5d3-nfc-io", "syscon"; 208 reg = <0xc0000000 0x8000000>; 209 }; 210 211 apb { 212 compatible = "simple-bus"; 213 #address-cells = <1>; 214 #size-cells = <1>; 215 ranges; 216 217 hlcdc: hlcdc@f0000000 { 218 compatible = "atmel,sama5d2-hlcdc"; 219 reg = <0xf0000000 0x2000>; 220 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 221 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 222 clock-names = "periph_clk","sys_clk", "slow_clk"; 223 status = "disabled"; 224 225 hlcdc-display-controller { 226 compatible = "atmel,hlcdc-display-controller"; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 230 port@0 { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 reg = <0>; 234 }; 235 }; 236 237 hlcdc_pwm: hlcdc-pwm { 238 compatible = "atmel,hlcdc-pwm"; 239 #pwm-cells = <3>; 240 }; 241 }; 242 243 isc: isc@f0008000 { 244 compatible = "atmel,sama5d2-isc"; 245 reg = <0xf0008000 0x4000>; 246 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 247 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 248 clock-names = "hclock", "iscck", "gck"; 249 #clock-cells = <0>; 250 clock-output-names = "isc-mck"; 251 status = "disabled"; 252 }; 253 254 ramc0: ramc@f000c000 { 255 compatible = "atmel,sama5d3-ddramc"; 256 reg = <0xf000c000 0x200>; 257 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 258 clock-names = "ddrck", "mpddr"; 259 }; 260 261 dma0: dma-controller@f0010000 { 262 compatible = "atmel,sama5d4-dma"; 263 reg = <0xf0010000 0x1000>; 264 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 265 #dma-cells = <1>; 266 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 267 clock-names = "dma_clk"; 268 }; 269 270 /* Place dma1 here despite its address */ 271 dma1: dma-controller@f0004000 { 272 compatible = "atmel,sama5d4-dma"; 273 reg = <0xf0004000 0x1000>; 274 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 275 #dma-cells = <1>; 276 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 277 clock-names = "dma_clk"; 278 }; 279 280 pmc: pmc@f0014000 { 281 compatible = "atmel,sama5d2-pmc", "syscon"; 282 reg = <0xf0014000 0x160>; 283 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 284 #clock-cells = <2>; 285 clocks = <&clk32k>, <&main_xtal>; 286 clock-names = "slow_clk", "main_xtal"; 287 }; 288 289 qspi0: spi@f0020000 { 290 compatible = "atmel,sama5d2-qspi"; 291 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 292 reg-names = "qspi_base", "qspi_mmap"; 293 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 294 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 status = "disabled"; 298 }; 299 300 qspi1: spi@f0024000 { 301 compatible = "atmel,sama5d2-qspi"; 302 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 303 reg-names = "qspi_base", "qspi_mmap"; 304 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 305 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 status = "disabled"; 309 }; 310 311 sha@f0028000 { 312 compatible = "atmel,at91sam9g46-sha"; 313 reg = <0xf0028000 0x100>; 314 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 315 dmas = <&dma0 316 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 317 AT91_XDMAC_DT_PERID(30))>; 318 dma-names = "tx"; 319 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 320 clock-names = "sha_clk"; 321 status = "okay"; 322 }; 323 324 aes@f002c000 { 325 compatible = "atmel,at91sam9g46-aes"; 326 reg = <0xf002c000 0x100>; 327 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 328 dmas = <&dma0 329 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 330 AT91_XDMAC_DT_PERID(26))>, 331 <&dma0 332 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 333 AT91_XDMAC_DT_PERID(27))>; 334 dma-names = "tx", "rx"; 335 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 336 clock-names = "aes_clk"; 337 status = "okay"; 338 }; 339 340 spi0: spi@f8000000 { 341 compatible = "atmel,at91rm9200-spi"; 342 reg = <0xf8000000 0x100>; 343 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 344 dmas = <&dma0 345 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 346 AT91_XDMAC_DT_PERID(6))>, 347 <&dma0 348 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 349 AT91_XDMAC_DT_PERID(7))>; 350 dma-names = "tx", "rx"; 351 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 352 clock-names = "spi_clk"; 353 atmel,fifo-size = <16>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 status = "disabled"; 357 }; 358 359 ssc0: ssc@f8004000 { 360 compatible = "atmel,at91sam9g45-ssc"; 361 reg = <0xf8004000 0x4000>; 362 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 363 dmas = <&dma0 364 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 365 AT91_XDMAC_DT_PERID(21))>, 366 <&dma0 367 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 368 AT91_XDMAC_DT_PERID(22))>; 369 dma-names = "tx", "rx"; 370 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 371 clock-names = "pclk"; 372 status = "disabled"; 373 }; 374 375 macb0: ethernet@f8008000 { 376 compatible = "atmel,sama5d2-gem"; 377 reg = <0xf8008000 0x1000>; 378 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 379 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 380 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 384 clock-names = "hclk", "pclk"; 385 status = "disabled"; 386 }; 387 388 tcb0: timer@f800c000 { 389 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 reg = <0xf800c000 0x100>; 393 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 394 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 395 clock-names = "t0_clk", "gclk", "slow_clk"; 396 }; 397 398 tcb1: timer@f8010000 { 399 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 reg = <0xf8010000 0x100>; 403 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 404 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 405 clock-names = "t0_clk", "gclk", "slow_clk"; 406 }; 407 408 hsmc: hsmc@f8014000 { 409 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 410 reg = <0xf8014000 0x1000>; 411 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 412 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 413 #address-cells = <1>; 414 #size-cells = <1>; 415 ranges; 416 417 pmecc: ecc-engine@f8014070 { 418 compatible = "atmel,sama5d2-pmecc"; 419 reg = <0xf8014070 0x490>, 420 <0xf8014500 0x100>; 421 }; 422 }; 423 424 pdmic: pdmic@f8018000 { 425 compatible = "atmel,sama5d2-pdmic"; 426 reg = <0xf8018000 0x124>; 427 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 428 dmas = <&dma0 429 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 430 | AT91_XDMAC_DT_PERID(50))>; 431 dma-names = "rx"; 432 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 433 clock-names = "pclk", "gclk"; 434 status = "disabled"; 435 }; 436 437 uart0: serial@f801c000 { 438 compatible = "atmel,at91sam9260-usart"; 439 reg = <0xf801c000 0x100>; 440 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 441 dmas = <&dma0 442 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 443 AT91_XDMAC_DT_PERID(35))>, 444 <&dma0 445 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 446 AT91_XDMAC_DT_PERID(36))>; 447 dma-names = "tx", "rx"; 448 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 449 clock-names = "usart"; 450 status = "disabled"; 451 }; 452 453 uart1: serial@f8020000 { 454 compatible = "atmel,at91sam9260-usart"; 455 reg = <0xf8020000 0x100>; 456 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 457 dmas = <&dma0 458 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 459 AT91_XDMAC_DT_PERID(37))>, 460 <&dma0 461 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 462 AT91_XDMAC_DT_PERID(38))>; 463 dma-names = "tx", "rx"; 464 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 465 clock-names = "usart"; 466 status = "disabled"; 467 }; 468 469 uart2: serial@f8024000 { 470 compatible = "atmel,at91sam9260-usart"; 471 reg = <0xf8024000 0x100>; 472 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 473 dmas = <&dma0 474 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 475 AT91_XDMAC_DT_PERID(39))>, 476 <&dma0 477 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 478 AT91_XDMAC_DT_PERID(40))>; 479 dma-names = "tx", "rx"; 480 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 481 clock-names = "usart"; 482 status = "disabled"; 483 }; 484 485 i2c0: i2c@f8028000 { 486 compatible = "atmel,sama5d2-i2c"; 487 reg = <0xf8028000 0x100>; 488 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 489 dmas = <&dma0 490 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 491 AT91_XDMAC_DT_PERID(0))>, 492 <&dma0 493 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 494 AT91_XDMAC_DT_PERID(1))>; 495 dma-names = "tx", "rx"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 499 atmel,fifo-size = <16>; 500 status = "disabled"; 501 }; 502 503 pwm0: pwm@f802c000 { 504 compatible = "atmel,sama5d2-pwm"; 505 reg = <0xf802c000 0x4000>; 506 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 507 #pwm-cells = <3>; 508 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 509 status = "disabled"; 510 }; 511 512 sfr: sfr@f8030000 { 513 compatible = "atmel,sama5d2-sfr", "syscon"; 514 reg = <0xf8030000 0x98>; 515 }; 516 517 flx0: flexcom@f8034000 { 518 compatible = "atmel,sama5d2-flexcom"; 519 reg = <0xf8034000 0x200>; 520 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 521 #address-cells = <1>; 522 #size-cells = <1>; 523 ranges = <0x0 0xf8034000 0x800>; 524 status = "disabled"; 525 526 uart5: serial@200 { 527 compatible = "atmel,at91sam9260-usart"; 528 reg = <0x200 0x200>; 529 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 530 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 531 clock-names = "usart"; 532 dmas = <&dma0 533 (AT91_XDMAC_DT_MEM_IF(0) | 534 AT91_XDMAC_DT_PER_IF(1) | 535 AT91_XDMAC_DT_PERID(11))>, 536 <&dma0 537 (AT91_XDMAC_DT_MEM_IF(0) | 538 AT91_XDMAC_DT_PER_IF(1) | 539 AT91_XDMAC_DT_PERID(12))>; 540 dma-names = "tx", "rx"; 541 atmel,fifo-size = <32>; 542 status = "disabled"; 543 }; 544 545 spi2: spi@400 { 546 compatible = "atmel,at91rm9200-spi"; 547 reg = <0x400 0x200>; 548 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 552 clock-names = "spi_clk"; 553 dmas = <&dma0 554 (AT91_XDMAC_DT_MEM_IF(0) | 555 AT91_XDMAC_DT_PER_IF(1) | 556 AT91_XDMAC_DT_PERID(11))>, 557 <&dma0 558 (AT91_XDMAC_DT_MEM_IF(0) | 559 AT91_XDMAC_DT_PER_IF(1) | 560 AT91_XDMAC_DT_PERID(12))>; 561 dma-names = "tx", "rx"; 562 atmel,fifo-size = <16>; 563 status = "disabled"; 564 }; 565 566 i2c2: i2c@600 { 567 compatible = "atmel,sama5d2-i2c"; 568 reg = <0x600 0x200>; 569 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 573 dmas = <&dma0 574 (AT91_XDMAC_DT_MEM_IF(0) | 575 AT91_XDMAC_DT_PER_IF(1) | 576 AT91_XDMAC_DT_PERID(11))>, 577 <&dma0 578 (AT91_XDMAC_DT_MEM_IF(0) | 579 AT91_XDMAC_DT_PER_IF(1) | 580 AT91_XDMAC_DT_PERID(12))>; 581 dma-names = "tx", "rx"; 582 atmel,fifo-size = <16>; 583 status = "disabled"; 584 }; 585 }; 586 587 flx1: flexcom@f8038000 { 588 compatible = "atmel,sama5d2-flexcom"; 589 reg = <0xf8038000 0x200>; 590 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges = <0x0 0xf8038000 0x800>; 594 status = "disabled"; 595 596 uart6: serial@200 { 597 compatible = "atmel,at91sam9260-usart"; 598 reg = <0x200 0x200>; 599 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 600 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 601 clock-names = "usart"; 602 dmas = <&dma0 603 (AT91_XDMAC_DT_MEM_IF(0) | 604 AT91_XDMAC_DT_PER_IF(1) | 605 AT91_XDMAC_DT_PERID(13))>, 606 <&dma0 607 (AT91_XDMAC_DT_MEM_IF(0) | 608 AT91_XDMAC_DT_PER_IF(1) | 609 AT91_XDMAC_DT_PERID(14))>; 610 dma-names = "tx", "rx"; 611 atmel,fifo-size = <32>; 612 status = "disabled"; 613 }; 614 615 spi3: spi@400 { 616 compatible = "atmel,at91rm9200-spi"; 617 reg = <0x400 0x200>; 618 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 622 clock-names = "spi_clk"; 623 dmas = <&dma0 624 (AT91_XDMAC_DT_MEM_IF(0) | 625 AT91_XDMAC_DT_PER_IF(1) | 626 AT91_XDMAC_DT_PERID(13))>, 627 <&dma0 628 (AT91_XDMAC_DT_MEM_IF(0) | 629 AT91_XDMAC_DT_PER_IF(1) | 630 AT91_XDMAC_DT_PERID(14))>; 631 dma-names = "tx", "rx"; 632 atmel,fifo-size = <16>; 633 status = "disabled"; 634 }; 635 636 i2c3: i2c@600 { 637 compatible = "atmel,sama5d2-i2c"; 638 reg = <0x600 0x200>; 639 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 643 dmas = <&dma0 644 (AT91_XDMAC_DT_MEM_IF(0) | 645 AT91_XDMAC_DT_PER_IF(1) | 646 AT91_XDMAC_DT_PERID(13))>, 647 <&dma0 648 (AT91_XDMAC_DT_MEM_IF(0) | 649 AT91_XDMAC_DT_PER_IF(1) | 650 AT91_XDMAC_DT_PERID(14))>; 651 dma-names = "tx", "rx"; 652 atmel,fifo-size = <16>; 653 status = "disabled"; 654 }; 655 }; 656 657 securam: sram@f8044000 { 658 compatible = "atmel,sama5d2-securam", "mmio-sram"; 659 reg = <0xf8044000 0x1420>; 660 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 661 #address-cells = <1>; 662 #size-cells = <1>; 663 no-memory-wc; 664 ranges = <0 0xf8044000 0x1420>; 665 status = "disabled"; 666 secure-status = "okay"; 667 }; 668 669 reset_controller: rstc@f8048000 { 670 compatible = "atmel,sama5d3-rstc"; 671 reg = <0xf8048000 0x10>; 672 clocks = <&clk32k>; 673 }; 674 675 shutdown_controller: shdwc@f8048010 { 676 compatible = "atmel,sama5d2-shdwc"; 677 reg = <0xf8048010 0x10>; 678 clocks = <&clk32k>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 atmel,wakeup-rtc-timer; 682 }; 683 684 pit: timer@f8048030 { 685 compatible = "atmel,at91sam9260-pit"; 686 reg = <0xf8048030 0x10>; 687 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 688 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 689 }; 690 691 watchdog: watchdog@f8048040 { 692 compatible = "atmel,sama5d4-wdt"; 693 reg = <0xf8048040 0x10>; 694 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 695 clocks = <&clk32k>; 696 status = "disabled"; 697 }; 698 699 clk32k: sckc@f8048050 { 700 compatible = "atmel,sama5d4-sckc"; 701 reg = <0xf8048050 0x4>; 702 703 clocks = <&slow_xtal>; 704 #clock-cells = <0>; 705 }; 706 707 rtc: rtc@f80480b0 { 708 compatible = "atmel,sama5d2-rtc"; 709 reg = <0xf80480b0 0x30>; 710 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 711 clocks = <&clk32k>; 712 }; 713 714 i2s0: i2s@f8050000 { 715 compatible = "atmel,sama5d2-i2s"; 716 reg = <0xf8050000 0x100>; 717 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 718 dmas = <&dma0 719 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 720 AT91_XDMAC_DT_PERID(31))>, 721 <&dma0 722 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 723 AT91_XDMAC_DT_PERID(32))>; 724 dma-names = "tx", "rx"; 725 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 726 clock-names = "pclk", "gclk"; 727 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 728 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 729 status = "disabled"; 730 }; 731 732 can0: can@f8054000 { 733 compatible = "bosch,m_can"; 734 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 735 reg-names = "m_can", "message_ram"; 736 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 737 <64 IRQ_TYPE_LEVEL_HIGH 7>; 738 interrupt-names = "int0", "int1"; 739 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 740 clock-names = "hclk", "cclk"; 741 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 742 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 743 assigned-clock-rates = <40000000>; 744 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 745 status = "disabled"; 746 }; 747 748 spi1: spi@fc000000 { 749 compatible = "atmel,at91rm9200-spi"; 750 reg = <0xfc000000 0x100>; 751 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 752 dmas = <&dma0 753 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 754 AT91_XDMAC_DT_PERID(8))>, 755 <&dma0 756 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 757 AT91_XDMAC_DT_PERID(9))>; 758 dma-names = "tx", "rx"; 759 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 760 clock-names = "spi_clk"; 761 atmel,fifo-size = <16>; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 status = "disabled"; 765 }; 766 767 uart3: serial@fc008000 { 768 compatible = "atmel,at91sam9260-usart"; 769 reg = <0xfc008000 0x100>; 770 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 771 dmas = <&dma1 772 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 773 AT91_XDMAC_DT_PERID(41))>, 774 <&dma1 775 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 776 AT91_XDMAC_DT_PERID(42))>; 777 dma-names = "tx", "rx"; 778 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 779 clock-names = "usart"; 780 status = "disabled"; 781 }; 782 783 uart4: serial@fc00c000 { 784 compatible = "atmel,at91sam9260-usart"; 785 reg = <0xfc00c000 0x100>; 786 dmas = <&dma0 787 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 788 AT91_XDMAC_DT_PERID(43))>, 789 <&dma0 790 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 791 AT91_XDMAC_DT_PERID(44))>; 792 dma-names = "tx", "rx"; 793 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 794 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 795 clock-names = "usart"; 796 status = "disabled"; 797 }; 798 799 flx2: flexcom@fc010000 { 800 compatible = "atmel,sama5d2-flexcom"; 801 reg = <0xfc010000 0x200>; 802 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 803 #address-cells = <1>; 804 #size-cells = <1>; 805 ranges = <0x0 0xfc010000 0x800>; 806 status = "disabled"; 807 808 uart7: serial@200 { 809 compatible = "atmel,at91sam9260-usart"; 810 reg = <0x200 0x200>; 811 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 812 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 813 clock-names = "usart"; 814 dmas = <&dma0 815 (AT91_XDMAC_DT_MEM_IF(0) | 816 AT91_XDMAC_DT_PER_IF(1) | 817 AT91_XDMAC_DT_PERID(15))>, 818 <&dma0 819 (AT91_XDMAC_DT_MEM_IF(0) | 820 AT91_XDMAC_DT_PER_IF(1) | 821 AT91_XDMAC_DT_PERID(16))>; 822 dma-names = "tx", "rx"; 823 atmel,fifo-size = <32>; 824 status = "disabled"; 825 }; 826 827 spi4: spi@400 { 828 compatible = "atmel,at91rm9200-spi"; 829 reg = <0x400 0x200>; 830 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 831 #address-cells = <1>; 832 #size-cells = <0>; 833 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 834 clock-names = "spi_clk"; 835 dmas = <&dma0 836 (AT91_XDMAC_DT_MEM_IF(0) | 837 AT91_XDMAC_DT_PER_IF(1) | 838 AT91_XDMAC_DT_PERID(15))>, 839 <&dma0 840 (AT91_XDMAC_DT_MEM_IF(0) | 841 AT91_XDMAC_DT_PER_IF(1) | 842 AT91_XDMAC_DT_PERID(16))>; 843 dma-names = "tx", "rx"; 844 atmel,fifo-size = <16>; 845 status = "disabled"; 846 }; 847 848 i2c4: i2c@600 { 849 compatible = "atmel,sama5d2-i2c"; 850 reg = <0x600 0x200>; 851 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 855 dmas = <&dma0 856 (AT91_XDMAC_DT_MEM_IF(0) | 857 AT91_XDMAC_DT_PER_IF(1) | 858 AT91_XDMAC_DT_PERID(15))>, 859 <&dma0 860 (AT91_XDMAC_DT_MEM_IF(0) | 861 AT91_XDMAC_DT_PER_IF(1) | 862 AT91_XDMAC_DT_PERID(16))>; 863 dma-names = "tx", "rx"; 864 atmel,fifo-size = <16>; 865 status = "disabled"; 866 }; 867 }; 868 869 flx3: flexcom@fc014000 { 870 compatible = "atmel,sama5d2-flexcom"; 871 reg = <0xfc014000 0x200>; 872 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 873 #address-cells = <1>; 874 #size-cells = <1>; 875 ranges = <0x0 0xfc014000 0x800>; 876 status = "disabled"; 877 878 uart8: serial@200 { 879 compatible = "atmel,at91sam9260-usart"; 880 reg = <0x200 0x200>; 881 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 882 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 883 clock-names = "usart"; 884 dmas = <&dma0 885 (AT91_XDMAC_DT_MEM_IF(0) | 886 AT91_XDMAC_DT_PER_IF(1) | 887 AT91_XDMAC_DT_PERID(17))>, 888 <&dma0 889 (AT91_XDMAC_DT_MEM_IF(0) | 890 AT91_XDMAC_DT_PER_IF(1) | 891 AT91_XDMAC_DT_PERID(18))>; 892 dma-names = "tx", "rx"; 893 atmel,fifo-size = <32>; 894 status = "disabled"; 895 }; 896 897 spi5: spi@400 { 898 compatible = "atmel,at91rm9200-spi"; 899 reg = <0x400 0x200>; 900 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 904 clock-names = "spi_clk"; 905 dmas = <&dma0 906 (AT91_XDMAC_DT_MEM_IF(0) | 907 AT91_XDMAC_DT_PER_IF(1) | 908 AT91_XDMAC_DT_PERID(17))>, 909 <&dma0 910 (AT91_XDMAC_DT_MEM_IF(0) | 911 AT91_XDMAC_DT_PER_IF(1) | 912 AT91_XDMAC_DT_PERID(18))>; 913 dma-names = "tx", "rx"; 914 atmel,fifo-size = <16>; 915 status = "disabled"; 916 }; 917 918 i2c5: i2c@600 { 919 compatible = "atmel,sama5d2-i2c"; 920 reg = <0x600 0x200>; 921 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 925 dmas = <&dma0 926 (AT91_XDMAC_DT_MEM_IF(0) | 927 AT91_XDMAC_DT_PER_IF(1) | 928 AT91_XDMAC_DT_PERID(17))>, 929 <&dma0 930 (AT91_XDMAC_DT_MEM_IF(0) | 931 AT91_XDMAC_DT_PER_IF(1) | 932 AT91_XDMAC_DT_PERID(18))>; 933 dma-names = "tx", "rx"; 934 atmel,fifo-size = <16>; 935 status = "disabled"; 936 }; 937 938 }; 939 940 flx4: flexcom@fc018000 { 941 compatible = "atmel,sama5d2-flexcom"; 942 reg = <0xfc018000 0x200>; 943 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 ranges = <0x0 0xfc018000 0x800>; 947 status = "disabled"; 948 949 uart9: serial@200 { 950 compatible = "atmel,at91sam9260-usart"; 951 reg = <0x200 0x200>; 952 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 953 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 954 clock-names = "usart"; 955 dmas = <&dma0 956 (AT91_XDMAC_DT_MEM_IF(0) | 957 AT91_XDMAC_DT_PER_IF(1) | 958 AT91_XDMAC_DT_PERID(19))>, 959 <&dma0 960 (AT91_XDMAC_DT_MEM_IF(0) | 961 AT91_XDMAC_DT_PER_IF(1) | 962 AT91_XDMAC_DT_PERID(20))>; 963 dma-names = "tx", "rx"; 964 atmel,fifo-size = <32>; 965 status = "disabled"; 966 }; 967 968 spi6: spi@400 { 969 compatible = "atmel,at91rm9200-spi"; 970 reg = <0x400 0x200>; 971 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 975 clock-names = "spi_clk"; 976 dmas = <&dma0 977 (AT91_XDMAC_DT_MEM_IF(0) | 978 AT91_XDMAC_DT_PER_IF(1) | 979 AT91_XDMAC_DT_PERID(19))>, 980 <&dma0 981 (AT91_XDMAC_DT_MEM_IF(0) | 982 AT91_XDMAC_DT_PER_IF(1) | 983 AT91_XDMAC_DT_PERID(20))>; 984 dma-names = "tx", "rx"; 985 atmel,fifo-size = <16>; 986 status = "disabled"; 987 }; 988 989 i2c6: i2c@600 { 990 compatible = "atmel,sama5d2-i2c"; 991 reg = <0x600 0x200>; 992 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 996 dmas = <&dma0 997 (AT91_XDMAC_DT_MEM_IF(0) | 998 AT91_XDMAC_DT_PER_IF(1) | 999 AT91_XDMAC_DT_PERID(19))>, 1000 <&dma0 1001 (AT91_XDMAC_DT_MEM_IF(0) | 1002 AT91_XDMAC_DT_PER_IF(1) | 1003 AT91_XDMAC_DT_PERID(20))>; 1004 dma-names = "tx", "rx"; 1005 atmel,fifo-size = <16>; 1006 status = "disabled"; 1007 }; 1008 }; 1009 1010 trng@fc01c000 { 1011 compatible = "atmel,at91sam9g45-trng"; 1012 reg = <0xfc01c000 0x100>; 1013 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1014 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1015 status = "disabled"; 1016 secure-status = "okay"; 1017 }; 1018 1019 aic: interrupt-controller@fc020000 { 1020 #interrupt-cells = <3>; 1021 compatible = "atmel,sama5d2-aic"; 1022 interrupt-controller; 1023 reg = <0xfc020000 0x200>; 1024 atmel,external-irqs = <49>; 1025 }; 1026 1027 i2c1: i2c@fc028000 { 1028 compatible = "atmel,sama5d2-i2c"; 1029 reg = <0xfc028000 0x100>; 1030 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1031 dmas = <&dma0 1032 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1033 AT91_XDMAC_DT_PERID(2))>, 1034 <&dma0 1035 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1036 AT91_XDMAC_DT_PERID(3))>; 1037 dma-names = "tx", "rx"; 1038 #address-cells = <1>; 1039 #size-cells = <0>; 1040 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1041 atmel,fifo-size = <16>; 1042 status = "disabled"; 1043 }; 1044 1045 adc: adc@fc030000 { 1046 compatible = "atmel,sama5d2-adc"; 1047 reg = <0xfc030000 0x100>; 1048 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1049 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1050 clock-names = "adc_clk"; 1051 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1052 dma-names = "rx"; 1053 atmel,min-sample-rate-hz = <200000>; 1054 atmel,max-sample-rate-hz = <20000000>; 1055 atmel,startup-time-ms = <4>; 1056 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1057 #io-channel-cells = <1>; 1058 status = "disabled"; 1059 }; 1060 1061 resistive_touch: resistive-touch { 1062 compatible = "resistive-adc-touch"; 1063 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1064 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1065 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1066 io-channel-names = "x", "y", "pressure"; 1067 touchscreen-min-pressure = <50000>; 1068 status = "disabled"; 1069 }; 1070 1071 pioA: pinctrl@fc038000 { 1072 compatible = "atmel,sama5d2-pinctrl"; 1073 reg = <0xfc038000 0x600>; 1074 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1075 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1076 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1077 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1078 interrupt-controller; 1079 #interrupt-cells = <2>; 1080 gpio-controller; 1081 #gpio-cells = <2>; 1082 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1083 }; 1084 1085 pioBU: secumod@fc040000 { 1086 compatible = "atmel,sama5d2-secumod", "syscon"; 1087 reg = <0xfc040000 0x100>; 1088 1089 gpio-controller; 1090 #gpio-cells = <2>; 1091 status = "disabled"; 1092 secure-status = "okay"; 1093 }; 1094 1095 tdes@fc044000 { 1096 compatible = "atmel,at91sam9g46-tdes"; 1097 reg = <0xfc044000 0x100>; 1098 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1099 dmas = <&dma0 1100 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1101 AT91_XDMAC_DT_PERID(28))>, 1102 <&dma0 1103 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1104 AT91_XDMAC_DT_PERID(29))>; 1105 dma-names = "tx", "rx"; 1106 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1107 clock-names = "tdes_clk"; 1108 status = "okay"; 1109 }; 1110 1111 classd: classd@fc048000 { 1112 compatible = "atmel,sama5d2-classd"; 1113 reg = <0xfc048000 0x100>; 1114 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1115 dmas = <&dma0 1116 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1117 AT91_XDMAC_DT_PERID(47))>; 1118 dma-names = "tx"; 1119 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1120 clock-names = "pclk", "gclk"; 1121 status = "disabled"; 1122 }; 1123 1124 i2s1: i2s@fc04c000 { 1125 compatible = "atmel,sama5d2-i2s"; 1126 reg = <0xfc04c000 0x100>; 1127 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1128 dmas = <&dma0 1129 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1130 AT91_XDMAC_DT_PERID(33))>, 1131 <&dma0 1132 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1133 AT91_XDMAC_DT_PERID(34))>; 1134 dma-names = "tx", "rx"; 1135 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1136 clock-names = "pclk", "gclk"; 1137 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1138 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1139 status = "disabled"; 1140 }; 1141 1142 can1: can@fc050000 { 1143 compatible = "bosch,m_can"; 1144 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1145 reg-names = "m_can", "message_ram"; 1146 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1147 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1148 interrupt-names = "int0", "int1"; 1149 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1150 clock-names = "hclk", "cclk"; 1151 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1152 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1153 assigned-clock-rates = <40000000>; 1154 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1155 status = "disabled"; 1156 }; 1157 1158 sfrbu: sfr@fc05c000 { 1159 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1160 reg = <0xfc05c000 0x20>; 1161 }; 1162 1163 chipid@fc069000 { 1164 compatible = "atmel,sama5d2-chipid"; 1165 reg = <0xfc069000 0x8>; 1166 }; 1167 }; 1168 }; 1169}; 1170