1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 clocks = <&pmc PMC_TYPE_CORE PMC_MCK_PRES>; 36 clock-names = "cpu"; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a5-pmu"; 42 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 43 }; 44 45 etb@740000 { 46 compatible = "arm,coresight-etb10", "arm,primecell"; 47 reg = <0x740000 0x1000>; 48 49 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 50 clock-names = "apb_pclk"; 51 52 in-ports { 53 port { 54 etb_in: endpoint { 55 remote-endpoint = <&etm_out>; 56 }; 57 }; 58 }; 59 }; 60 61 etm@73c000 { 62 compatible = "arm,coresight-etm3x", "arm,primecell"; 63 reg = <0x73c000 0x1000>; 64 65 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 66 clock-names = "apb_pclk"; 67 68 out-ports { 69 port { 70 etm_out: endpoint { 71 remote-endpoint = <&etb_in>; 72 }; 73 }; 74 }; 75 }; 76 77 memory@20000000 { 78 device_type = "memory"; 79 reg = <0x20000000 0x20000000>; 80 }; 81 82 clocks { 83 slow_xtal: slow_xtal { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <0>; 87 }; 88 89 main_xtal: main_xtal { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 }; 94 }; 95 96 ns_sram: sram@200000 { 97 compatible = "atmel,sama5d2-sram", "mmio-sram"; 98 reg = <0x00200000 0x20000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x00200000 0x20000>; 102 status = "disabled"; 103 secure-status = "okay"; 104 }; 105 106 ahb { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 112 nfc_sram: sram@100000 { 113 compatible = "mmio-sram"; 114 no-memory-wc; 115 reg = <0x00100000 0x2400>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x00100000 0x2400>; 119 120 }; 121 122 usb0: gadget@300000 { 123 compatible = "atmel,sama5d3-udc"; 124 reg = <0x00300000 0x100000 125 0xfc02c000 0x400>; 126 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 127 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 128 clock-names = "pclk", "hclk"; 129 status = "disabled"; 130 }; 131 132 usb1: ohci@400000 { 133 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 134 reg = <0x00400000 0x100000>; 135 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 136 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 137 clock-names = "ohci_clk", "hclk", "uhpck"; 138 status = "disabled"; 139 }; 140 141 usb2: ehci@500000 { 142 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 143 reg = <0x00500000 0x100000>; 144 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 145 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 146 clock-names = "usb_clk", "ehci_clk"; 147 status = "disabled"; 148 }; 149 150 L2: cache-controller@a00000 { 151 compatible = "arm,pl310-cache"; 152 reg = <0x00a00000 0x1000>; 153 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 154 cache-unified; 155 cache-level = <2>; 156 }; 157 158 ebi: ebi@10000000 { 159 compatible = "atmel,sama5d3-ebi"; 160 #address-cells = <2>; 161 #size-cells = <1>; 162 atmel,smc = <&hsmc>; 163 reg = <0x10000000 0x10000000 164 0x60000000 0x30000000>; 165 ranges = <0x0 0x0 0x10000000 0x10000000 166 0x1 0x0 0x60000000 0x10000000 167 0x2 0x0 0x70000000 0x10000000 168 0x3 0x0 0x80000000 0x10000000>; 169 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 170 status = "disabled"; 171 172 nand_controller: nand-controller { 173 compatible = "atmel,sama5d3-nand-controller"; 174 atmel,nfc-sram = <&nfc_sram>; 175 atmel,nfc-io = <&nfc_io>; 176 ecc-engine = <&pmecc>; 177 #address-cells = <2>; 178 #size-cells = <1>; 179 ranges; 180 status = "disabled"; 181 }; 182 }; 183 184 sdmmc0: sdio-host@a0000000 { 185 compatible = "atmel,sama5d2-sdhci"; 186 reg = <0xa0000000 0x300>; 187 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 188 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 189 clock-names = "hclock", "multclk", "baseclk"; 190 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 191 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 192 assigned-clock-rates = <480000000>; 193 status = "disabled"; 194 }; 195 196 sdmmc1: sdio-host@b0000000 { 197 compatible = "atmel,sama5d2-sdhci"; 198 reg = <0xb0000000 0x300>; 199 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 200 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 201 clock-names = "hclock", "multclk", "baseclk"; 202 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 203 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 204 assigned-clock-rates = <480000000>; 205 status = "disabled"; 206 }; 207 208 nfc_io: nfc-io@c0000000 { 209 compatible = "atmel,sama5d3-nfc-io", "syscon"; 210 reg = <0xc0000000 0x8000000>; 211 }; 212 213 apb { 214 compatible = "simple-bus"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges; 218 219 hlcdc: hlcdc@f0000000 { 220 compatible = "atmel,sama5d2-hlcdc"; 221 reg = <0xf0000000 0x2000>; 222 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 223 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 224 clock-names = "periph_clk","sys_clk", "slow_clk"; 225 status = "disabled"; 226 227 hlcdc-display-controller { 228 compatible = "atmel,hlcdc-display-controller"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 port@0 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0>; 236 }; 237 }; 238 239 hlcdc_pwm: hlcdc-pwm { 240 compatible = "atmel,hlcdc-pwm"; 241 #pwm-cells = <3>; 242 }; 243 }; 244 245 isc: isc@f0008000 { 246 compatible = "atmel,sama5d2-isc"; 247 reg = <0xf0008000 0x4000>; 248 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 249 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 250 clock-names = "hclock", "iscck", "gck"; 251 #clock-cells = <0>; 252 clock-output-names = "isc-mck"; 253 status = "disabled"; 254 }; 255 256 ramc0: ramc@f000c000 { 257 compatible = "atmel,sama5d3-ddramc"; 258 reg = <0xf000c000 0x200>; 259 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 260 clock-names = "ddrck", "mpddr"; 261 }; 262 263 dma0: dma-controller@f0010000 { 264 compatible = "atmel,sama5d4-dma"; 265 reg = <0xf0010000 0x1000>; 266 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 267 #dma-cells = <1>; 268 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 269 clock-names = "dma_clk"; 270 }; 271 272 /* Place dma1 here despite its address */ 273 dma1: dma-controller@f0004000 { 274 compatible = "atmel,sama5d4-dma"; 275 reg = <0xf0004000 0x1000>; 276 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 277 #dma-cells = <1>; 278 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 279 clock-names = "dma_clk"; 280 }; 281 282 pmc: pmc@f0014000 { 283 compatible = "atmel,sama5d2-pmc", "syscon"; 284 reg = <0xf0014000 0x160>; 285 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 286 #clock-cells = <2>; 287 clocks = <&clk32k>, <&main_xtal>; 288 clock-names = "slow_clk", "main_xtal"; 289 }; 290 291 qspi0: spi@f0020000 { 292 compatible = "atmel,sama5d2-qspi"; 293 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 294 reg-names = "qspi_base", "qspi_mmap"; 295 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 296 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 qspi1: spi@f0024000 { 303 compatible = "atmel,sama5d2-qspi"; 304 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 305 reg-names = "qspi_base", "qspi_mmap"; 306 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 307 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 status = "disabled"; 311 }; 312 313 sha@f0028000 { 314 compatible = "atmel,at91sam9g46-sha"; 315 reg = <0xf0028000 0x100>; 316 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 317 dmas = <&dma0 318 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 319 AT91_XDMAC_DT_PERID(30))>; 320 dma-names = "tx"; 321 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 322 clock-names = "sha_clk"; 323 status = "okay"; 324 }; 325 326 aes@f002c000 { 327 compatible = "atmel,at91sam9g46-aes"; 328 reg = <0xf002c000 0x100>; 329 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 330 dmas = <&dma0 331 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 332 AT91_XDMAC_DT_PERID(26))>, 333 <&dma0 334 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 335 AT91_XDMAC_DT_PERID(27))>; 336 dma-names = "tx", "rx"; 337 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 338 clock-names = "aes_clk"; 339 status = "okay"; 340 }; 341 342 spi0: spi@f8000000 { 343 compatible = "atmel,at91rm9200-spi"; 344 reg = <0xf8000000 0x100>; 345 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 346 dmas = <&dma0 347 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 348 AT91_XDMAC_DT_PERID(6))>, 349 <&dma0 350 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 351 AT91_XDMAC_DT_PERID(7))>; 352 dma-names = "tx", "rx"; 353 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 354 clock-names = "spi_clk"; 355 atmel,fifo-size = <16>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 status = "disabled"; 359 }; 360 361 ssc0: ssc@f8004000 { 362 compatible = "atmel,at91sam9g45-ssc"; 363 reg = <0xf8004000 0x4000>; 364 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 365 dmas = <&dma0 366 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 367 AT91_XDMAC_DT_PERID(21))>, 368 <&dma0 369 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 370 AT91_XDMAC_DT_PERID(22))>; 371 dma-names = "tx", "rx"; 372 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 373 clock-names = "pclk"; 374 status = "disabled"; 375 }; 376 377 macb0: ethernet@f8008000 { 378 compatible = "atmel,sama5d2-gem"; 379 reg = <0xf8008000 0x1000>; 380 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 381 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 382 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 383 #address-cells = <1>; 384 #size-cells = <0>; 385 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 386 clock-names = "hclk", "pclk"; 387 status = "disabled"; 388 }; 389 390 tcb0: timer@f800c000 { 391 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 reg = <0xf800c000 0x100>; 395 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 396 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 397 clock-names = "t0_clk", "gclk", "slow_clk"; 398 }; 399 400 tcb1: timer@f8010000 { 401 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 reg = <0xf8010000 0x100>; 405 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 406 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 407 clock-names = "t0_clk", "gclk", "slow_clk"; 408 status = "disabled"; 409 secure-status = "okay"; 410 }; 411 412 hsmc: hsmc@f8014000 { 413 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 414 reg = <0xf8014000 0x1000>; 415 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 416 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 417 #address-cells = <1>; 418 #size-cells = <1>; 419 ranges; 420 421 pmecc: ecc-engine@f8014070 { 422 compatible = "atmel,sama5d2-pmecc"; 423 reg = <0xf8014070 0x490>, 424 <0xf8014500 0x100>; 425 }; 426 }; 427 428 pdmic: pdmic@f8018000 { 429 compatible = "atmel,sama5d2-pdmic"; 430 reg = <0xf8018000 0x124>; 431 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 432 dmas = <&dma0 433 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 434 | AT91_XDMAC_DT_PERID(50))>; 435 dma-names = "rx"; 436 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 437 clock-names = "pclk", "gclk"; 438 status = "disabled"; 439 }; 440 441 uart0: serial@f801c000 { 442 compatible = "atmel,at91sam9260-usart"; 443 reg = <0xf801c000 0x100>; 444 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 445 dmas = <&dma0 446 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 447 AT91_XDMAC_DT_PERID(35))>, 448 <&dma0 449 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 450 AT91_XDMAC_DT_PERID(36))>; 451 dma-names = "tx", "rx"; 452 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 453 clock-names = "usart"; 454 status = "disabled"; 455 }; 456 457 uart1: serial@f8020000 { 458 compatible = "atmel,at91sam9260-usart"; 459 reg = <0xf8020000 0x100>; 460 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 461 dmas = <&dma0 462 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 463 AT91_XDMAC_DT_PERID(37))>, 464 <&dma0 465 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 466 AT91_XDMAC_DT_PERID(38))>; 467 dma-names = "tx", "rx"; 468 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 469 clock-names = "usart"; 470 status = "disabled"; 471 }; 472 473 uart2: serial@f8024000 { 474 compatible = "atmel,at91sam9260-usart"; 475 reg = <0xf8024000 0x100>; 476 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 477 dmas = <&dma0 478 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 479 AT91_XDMAC_DT_PERID(39))>, 480 <&dma0 481 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 482 AT91_XDMAC_DT_PERID(40))>; 483 dma-names = "tx", "rx"; 484 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 485 clock-names = "usart"; 486 status = "disabled"; 487 }; 488 489 i2c0: i2c@f8028000 { 490 compatible = "atmel,sama5d2-i2c"; 491 reg = <0xf8028000 0x100>; 492 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 493 dmas = <&dma0 494 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 495 AT91_XDMAC_DT_PERID(0))>, 496 <&dma0 497 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 498 AT91_XDMAC_DT_PERID(1))>; 499 dma-names = "tx", "rx"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 503 atmel,fifo-size = <16>; 504 status = "disabled"; 505 }; 506 507 pwm0: pwm@f802c000 { 508 compatible = "atmel,sama5d2-pwm"; 509 reg = <0xf802c000 0x4000>; 510 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 511 #pwm-cells = <3>; 512 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 513 status = "disabled"; 514 }; 515 516 sfr: sfr@f8030000 { 517 compatible = "atmel,sama5d2-sfr", "syscon"; 518 reg = <0xf8030000 0x98>; 519 }; 520 521 flx0: flexcom@f8034000 { 522 compatible = "atmel,sama5d2-flexcom"; 523 reg = <0xf8034000 0x200>; 524 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 525 #address-cells = <1>; 526 #size-cells = <1>; 527 ranges = <0x0 0xf8034000 0x800>; 528 status = "disabled"; 529 530 uart5: serial@200 { 531 compatible = "atmel,at91sam9260-usart"; 532 reg = <0x200 0x200>; 533 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 534 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 535 clock-names = "usart"; 536 dmas = <&dma0 537 (AT91_XDMAC_DT_MEM_IF(0) | 538 AT91_XDMAC_DT_PER_IF(1) | 539 AT91_XDMAC_DT_PERID(11))>, 540 <&dma0 541 (AT91_XDMAC_DT_MEM_IF(0) | 542 AT91_XDMAC_DT_PER_IF(1) | 543 AT91_XDMAC_DT_PERID(12))>; 544 dma-names = "tx", "rx"; 545 atmel,fifo-size = <32>; 546 status = "disabled"; 547 }; 548 549 spi2: spi@400 { 550 compatible = "atmel,at91rm9200-spi"; 551 reg = <0x400 0x200>; 552 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 556 clock-names = "spi_clk"; 557 dmas = <&dma0 558 (AT91_XDMAC_DT_MEM_IF(0) | 559 AT91_XDMAC_DT_PER_IF(1) | 560 AT91_XDMAC_DT_PERID(11))>, 561 <&dma0 562 (AT91_XDMAC_DT_MEM_IF(0) | 563 AT91_XDMAC_DT_PER_IF(1) | 564 AT91_XDMAC_DT_PERID(12))>; 565 dma-names = "tx", "rx"; 566 atmel,fifo-size = <16>; 567 status = "disabled"; 568 }; 569 570 i2c2: i2c@600 { 571 compatible = "atmel,sama5d2-i2c"; 572 reg = <0x600 0x200>; 573 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 577 dmas = <&dma0 578 (AT91_XDMAC_DT_MEM_IF(0) | 579 AT91_XDMAC_DT_PER_IF(1) | 580 AT91_XDMAC_DT_PERID(11))>, 581 <&dma0 582 (AT91_XDMAC_DT_MEM_IF(0) | 583 AT91_XDMAC_DT_PER_IF(1) | 584 AT91_XDMAC_DT_PERID(12))>; 585 dma-names = "tx", "rx"; 586 atmel,fifo-size = <16>; 587 status = "disabled"; 588 }; 589 }; 590 591 flx1: flexcom@f8038000 { 592 compatible = "atmel,sama5d2-flexcom"; 593 reg = <0xf8038000 0x200>; 594 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 595 #address-cells = <1>; 596 #size-cells = <1>; 597 ranges = <0x0 0xf8038000 0x800>; 598 status = "disabled"; 599 600 uart6: serial@200 { 601 compatible = "atmel,at91sam9260-usart"; 602 reg = <0x200 0x200>; 603 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 604 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 605 clock-names = "usart"; 606 dmas = <&dma0 607 (AT91_XDMAC_DT_MEM_IF(0) | 608 AT91_XDMAC_DT_PER_IF(1) | 609 AT91_XDMAC_DT_PERID(13))>, 610 <&dma0 611 (AT91_XDMAC_DT_MEM_IF(0) | 612 AT91_XDMAC_DT_PER_IF(1) | 613 AT91_XDMAC_DT_PERID(14))>; 614 dma-names = "tx", "rx"; 615 atmel,fifo-size = <32>; 616 status = "disabled"; 617 }; 618 619 spi3: spi@400 { 620 compatible = "atmel,at91rm9200-spi"; 621 reg = <0x400 0x200>; 622 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 626 clock-names = "spi_clk"; 627 dmas = <&dma0 628 (AT91_XDMAC_DT_MEM_IF(0) | 629 AT91_XDMAC_DT_PER_IF(1) | 630 AT91_XDMAC_DT_PERID(13))>, 631 <&dma0 632 (AT91_XDMAC_DT_MEM_IF(0) | 633 AT91_XDMAC_DT_PER_IF(1) | 634 AT91_XDMAC_DT_PERID(14))>; 635 dma-names = "tx", "rx"; 636 atmel,fifo-size = <16>; 637 status = "disabled"; 638 }; 639 640 i2c3: i2c@600 { 641 compatible = "atmel,sama5d2-i2c"; 642 reg = <0x600 0x200>; 643 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 644 #address-cells = <1>; 645 #size-cells = <0>; 646 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 647 dmas = <&dma0 648 (AT91_XDMAC_DT_MEM_IF(0) | 649 AT91_XDMAC_DT_PER_IF(1) | 650 AT91_XDMAC_DT_PERID(13))>, 651 <&dma0 652 (AT91_XDMAC_DT_MEM_IF(0) | 653 AT91_XDMAC_DT_PER_IF(1) | 654 AT91_XDMAC_DT_PERID(14))>; 655 dma-names = "tx", "rx"; 656 atmel,fifo-size = <16>; 657 status = "disabled"; 658 }; 659 }; 660 661 securam: sram@f8044000 { 662 compatible = "atmel,sama5d2-securam", "mmio-sram"; 663 reg = <0xf8044000 0x1420>; 664 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 665 #address-cells = <1>; 666 #size-cells = <1>; 667 no-memory-wc; 668 ranges = <0 0xf8044000 0x1420>; 669 status = "disabled"; 670 secure-status = "okay"; 671 }; 672 673 reset_controller: rstc@f8048000 { 674 compatible = "atmel,sama5d3-rstc"; 675 reg = <0xf8048000 0x10>; 676 clocks = <&clk32k>; 677 }; 678 679 shutdown_controller: shdwc@f8048010 { 680 compatible = "atmel,sama5d2-shdwc"; 681 reg = <0xf8048010 0x10>; 682 clocks = <&clk32k>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 atmel,wakeup-rtc-timer; 686 }; 687 688 pit: timer@f8048030 { 689 compatible = "atmel,at91sam9260-pit"; 690 reg = <0xf8048030 0x10>; 691 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 692 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 693 }; 694 695 watchdog: watchdog@f8048040 { 696 compatible = "atmel,sama5d4-wdt"; 697 reg = <0xf8048040 0x10>; 698 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 699 clocks = <&clk32k>; 700 status = "disabled"; 701 secure-status = "okay"; 702 }; 703 704 clk32k: sckc@f8048050 { 705 compatible = "atmel,sama5d4-sckc"; 706 reg = <0xf8048050 0x4>; 707 708 clocks = <&slow_xtal>; 709 #clock-cells = <0>; 710 }; 711 712 rtc: rtc@f80480b0 { 713 compatible = "atmel,sama5d2-rtc"; 714 reg = <0xf80480b0 0x30>; 715 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 716 clocks = <&clk32k>; 717 status = "disabled"; 718 secure-status = "okay"; 719 }; 720 721 i2s0: i2s@f8050000 { 722 compatible = "atmel,sama5d2-i2s"; 723 reg = <0xf8050000 0x100>; 724 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 725 dmas = <&dma0 726 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 727 AT91_XDMAC_DT_PERID(31))>, 728 <&dma0 729 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 730 AT91_XDMAC_DT_PERID(32))>; 731 dma-names = "tx", "rx"; 732 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 733 clock-names = "pclk", "gclk"; 734 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 735 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 736 status = "disabled"; 737 }; 738 739 can0: can@f8054000 { 740 compatible = "bosch,m_can"; 741 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 742 reg-names = "m_can", "message_ram"; 743 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 744 <64 IRQ_TYPE_LEVEL_HIGH 7>; 745 interrupt-names = "int0", "int1"; 746 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 747 clock-names = "hclk", "cclk"; 748 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 749 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 750 assigned-clock-rates = <40000000>; 751 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 752 status = "disabled"; 753 }; 754 755 spi1: spi@fc000000 { 756 compatible = "atmel,at91rm9200-spi"; 757 reg = <0xfc000000 0x100>; 758 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 759 dmas = <&dma0 760 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 761 AT91_XDMAC_DT_PERID(8))>, 762 <&dma0 763 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 764 AT91_XDMAC_DT_PERID(9))>; 765 dma-names = "tx", "rx"; 766 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 767 clock-names = "spi_clk"; 768 atmel,fifo-size = <16>; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 774 uart3: serial@fc008000 { 775 compatible = "atmel,at91sam9260-usart"; 776 reg = <0xfc008000 0x100>; 777 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 778 dmas = <&dma1 779 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 780 AT91_XDMAC_DT_PERID(41))>, 781 <&dma1 782 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 783 AT91_XDMAC_DT_PERID(42))>; 784 dma-names = "tx", "rx"; 785 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 786 clock-names = "usart"; 787 status = "disabled"; 788 }; 789 790 uart4: serial@fc00c000 { 791 compatible = "atmel,at91sam9260-usart"; 792 reg = <0xfc00c000 0x100>; 793 dmas = <&dma0 794 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 795 AT91_XDMAC_DT_PERID(43))>, 796 <&dma0 797 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 798 AT91_XDMAC_DT_PERID(44))>; 799 dma-names = "tx", "rx"; 800 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 801 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 802 clock-names = "usart"; 803 status = "disabled"; 804 }; 805 806 flx2: flexcom@fc010000 { 807 compatible = "atmel,sama5d2-flexcom"; 808 reg = <0xfc010000 0x200>; 809 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 ranges = <0x0 0xfc010000 0x800>; 813 status = "disabled"; 814 815 uart7: serial@200 { 816 compatible = "atmel,at91sam9260-usart"; 817 reg = <0x200 0x200>; 818 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 819 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 820 clock-names = "usart"; 821 dmas = <&dma0 822 (AT91_XDMAC_DT_MEM_IF(0) | 823 AT91_XDMAC_DT_PER_IF(1) | 824 AT91_XDMAC_DT_PERID(15))>, 825 <&dma0 826 (AT91_XDMAC_DT_MEM_IF(0) | 827 AT91_XDMAC_DT_PER_IF(1) | 828 AT91_XDMAC_DT_PERID(16))>; 829 dma-names = "tx", "rx"; 830 atmel,fifo-size = <32>; 831 status = "disabled"; 832 }; 833 834 spi4: spi@400 { 835 compatible = "atmel,at91rm9200-spi"; 836 reg = <0x400 0x200>; 837 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 841 clock-names = "spi_clk"; 842 dmas = <&dma0 843 (AT91_XDMAC_DT_MEM_IF(0) | 844 AT91_XDMAC_DT_PER_IF(1) | 845 AT91_XDMAC_DT_PERID(15))>, 846 <&dma0 847 (AT91_XDMAC_DT_MEM_IF(0) | 848 AT91_XDMAC_DT_PER_IF(1) | 849 AT91_XDMAC_DT_PERID(16))>; 850 dma-names = "tx", "rx"; 851 atmel,fifo-size = <16>; 852 status = "disabled"; 853 }; 854 855 i2c4: i2c@600 { 856 compatible = "atmel,sama5d2-i2c"; 857 reg = <0x600 0x200>; 858 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 862 dmas = <&dma0 863 (AT91_XDMAC_DT_MEM_IF(0) | 864 AT91_XDMAC_DT_PER_IF(1) | 865 AT91_XDMAC_DT_PERID(15))>, 866 <&dma0 867 (AT91_XDMAC_DT_MEM_IF(0) | 868 AT91_XDMAC_DT_PER_IF(1) | 869 AT91_XDMAC_DT_PERID(16))>; 870 dma-names = "tx", "rx"; 871 atmel,fifo-size = <16>; 872 status = "disabled"; 873 }; 874 }; 875 876 flx3: flexcom@fc014000 { 877 compatible = "atmel,sama5d2-flexcom"; 878 reg = <0xfc014000 0x200>; 879 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 880 #address-cells = <1>; 881 #size-cells = <1>; 882 ranges = <0x0 0xfc014000 0x800>; 883 status = "disabled"; 884 885 uart8: serial@200 { 886 compatible = "atmel,at91sam9260-usart"; 887 reg = <0x200 0x200>; 888 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 889 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 890 clock-names = "usart"; 891 dmas = <&dma0 892 (AT91_XDMAC_DT_MEM_IF(0) | 893 AT91_XDMAC_DT_PER_IF(1) | 894 AT91_XDMAC_DT_PERID(17))>, 895 <&dma0 896 (AT91_XDMAC_DT_MEM_IF(0) | 897 AT91_XDMAC_DT_PER_IF(1) | 898 AT91_XDMAC_DT_PERID(18))>; 899 dma-names = "tx", "rx"; 900 atmel,fifo-size = <32>; 901 status = "disabled"; 902 }; 903 904 spi5: spi@400 { 905 compatible = "atmel,at91rm9200-spi"; 906 reg = <0x400 0x200>; 907 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 911 clock-names = "spi_clk"; 912 dmas = <&dma0 913 (AT91_XDMAC_DT_MEM_IF(0) | 914 AT91_XDMAC_DT_PER_IF(1) | 915 AT91_XDMAC_DT_PERID(17))>, 916 <&dma0 917 (AT91_XDMAC_DT_MEM_IF(0) | 918 AT91_XDMAC_DT_PER_IF(1) | 919 AT91_XDMAC_DT_PERID(18))>; 920 dma-names = "tx", "rx"; 921 atmel,fifo-size = <16>; 922 status = "disabled"; 923 }; 924 925 i2c5: i2c@600 { 926 compatible = "atmel,sama5d2-i2c"; 927 reg = <0x600 0x200>; 928 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 929 #address-cells = <1>; 930 #size-cells = <0>; 931 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 932 dmas = <&dma0 933 (AT91_XDMAC_DT_MEM_IF(0) | 934 AT91_XDMAC_DT_PER_IF(1) | 935 AT91_XDMAC_DT_PERID(17))>, 936 <&dma0 937 (AT91_XDMAC_DT_MEM_IF(0) | 938 AT91_XDMAC_DT_PER_IF(1) | 939 AT91_XDMAC_DT_PERID(18))>; 940 dma-names = "tx", "rx"; 941 atmel,fifo-size = <16>; 942 status = "disabled"; 943 }; 944 945 }; 946 947 flx4: flexcom@fc018000 { 948 compatible = "atmel,sama5d2-flexcom"; 949 reg = <0xfc018000 0x200>; 950 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 951 #address-cells = <1>; 952 #size-cells = <1>; 953 ranges = <0x0 0xfc018000 0x800>; 954 status = "disabled"; 955 956 uart9: serial@200 { 957 compatible = "atmel,at91sam9260-usart"; 958 reg = <0x200 0x200>; 959 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 960 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 961 clock-names = "usart"; 962 dmas = <&dma0 963 (AT91_XDMAC_DT_MEM_IF(0) | 964 AT91_XDMAC_DT_PER_IF(1) | 965 AT91_XDMAC_DT_PERID(19))>, 966 <&dma0 967 (AT91_XDMAC_DT_MEM_IF(0) | 968 AT91_XDMAC_DT_PER_IF(1) | 969 AT91_XDMAC_DT_PERID(20))>; 970 dma-names = "tx", "rx"; 971 atmel,fifo-size = <32>; 972 status = "disabled"; 973 }; 974 975 spi6: spi@400 { 976 compatible = "atmel,at91rm9200-spi"; 977 reg = <0x400 0x200>; 978 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 982 clock-names = "spi_clk"; 983 dmas = <&dma0 984 (AT91_XDMAC_DT_MEM_IF(0) | 985 AT91_XDMAC_DT_PER_IF(1) | 986 AT91_XDMAC_DT_PERID(19))>, 987 <&dma0 988 (AT91_XDMAC_DT_MEM_IF(0) | 989 AT91_XDMAC_DT_PER_IF(1) | 990 AT91_XDMAC_DT_PERID(20))>; 991 dma-names = "tx", "rx"; 992 atmel,fifo-size = <16>; 993 status = "disabled"; 994 }; 995 996 i2c6: i2c@600 { 997 compatible = "atmel,sama5d2-i2c"; 998 reg = <0x600 0x200>; 999 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1003 dmas = <&dma0 1004 (AT91_XDMAC_DT_MEM_IF(0) | 1005 AT91_XDMAC_DT_PER_IF(1) | 1006 AT91_XDMAC_DT_PERID(19))>, 1007 <&dma0 1008 (AT91_XDMAC_DT_MEM_IF(0) | 1009 AT91_XDMAC_DT_PER_IF(1) | 1010 AT91_XDMAC_DT_PERID(20))>; 1011 dma-names = "tx", "rx"; 1012 atmel,fifo-size = <16>; 1013 status = "disabled"; 1014 }; 1015 }; 1016 1017 trng@fc01c000 { 1018 compatible = "atmel,at91sam9g45-trng"; 1019 reg = <0xfc01c000 0x100>; 1020 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1021 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1022 status = "disabled"; 1023 secure-status = "okay"; 1024 }; 1025 1026 aic: interrupt-controller@fc020000 { 1027 #interrupt-cells = <3>; 1028 compatible = "atmel,sama5d2-aic"; 1029 interrupt-controller; 1030 reg = <0xfc020000 0x200>; 1031 atmel,external-irqs = <49>; 1032 }; 1033 1034 saic: interrupt-controller@f803c000 { 1035 #interrupt-cells = <3>; 1036 compatible = "atmel,sama5d2-saic"; 1037 interrupt-controller; 1038 reg = <0xf803c000 0x200>; 1039 atmel,external-irqs = <49>; 1040 status = "disabled"; 1041 secure-status = "okay"; 1042 }; 1043 1044 i2c1: i2c@fc028000 { 1045 compatible = "atmel,sama5d2-i2c"; 1046 reg = <0xfc028000 0x100>; 1047 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1048 dmas = <&dma0 1049 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1050 AT91_XDMAC_DT_PERID(2))>, 1051 <&dma0 1052 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1053 AT91_XDMAC_DT_PERID(3))>; 1054 dma-names = "tx", "rx"; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1058 atmel,fifo-size = <16>; 1059 status = "disabled"; 1060 }; 1061 1062 adc: adc@fc030000 { 1063 compatible = "atmel,sama5d2-adc"; 1064 reg = <0xfc030000 0x100>; 1065 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1066 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1067 clock-names = "adc_clk"; 1068 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1069 dma-names = "rx"; 1070 atmel,min-sample-rate-hz = <200000>; 1071 atmel,max-sample-rate-hz = <20000000>; 1072 atmel,startup-time-ms = <4>; 1073 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1074 #io-channel-cells = <1>; 1075 status = "disabled"; 1076 }; 1077 1078 resistive_touch: resistive-touch { 1079 compatible = "resistive-adc-touch"; 1080 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1081 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1082 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1083 io-channel-names = "x", "y", "pressure"; 1084 touchscreen-min-pressure = <50000>; 1085 status = "disabled"; 1086 }; 1087 1088 pioA: pinctrl@fc038000 { 1089 compatible = "atmel,sama5d2-pinctrl"; 1090 reg = <0xfc038000 0x600>; 1091 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1092 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1093 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1094 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1095 interrupt-controller; 1096 #interrupt-cells = <2>; 1097 gpio-controller; 1098 #gpio-cells = <2>; 1099 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1100 }; 1101 1102 pioBU: secumod@fc040000 { 1103 compatible = "atmel,sama5d2-secumod", "syscon"; 1104 reg = <0xfc040000 0x100>; 1105 1106 gpio-controller; 1107 #gpio-cells = <2>; 1108 status = "disabled"; 1109 secure-status = "okay"; 1110 }; 1111 1112 tdes@fc044000 { 1113 compatible = "atmel,at91sam9g46-tdes"; 1114 reg = <0xfc044000 0x100>; 1115 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1116 dmas = <&dma0 1117 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1118 AT91_XDMAC_DT_PERID(28))>, 1119 <&dma0 1120 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1121 AT91_XDMAC_DT_PERID(29))>; 1122 dma-names = "tx", "rx"; 1123 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1124 clock-names = "tdes_clk"; 1125 status = "okay"; 1126 }; 1127 1128 classd: classd@fc048000 { 1129 compatible = "atmel,sama5d2-classd"; 1130 reg = <0xfc048000 0x100>; 1131 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1132 dmas = <&dma0 1133 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1134 AT91_XDMAC_DT_PERID(47))>; 1135 dma-names = "tx"; 1136 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1137 clock-names = "pclk", "gclk"; 1138 status = "disabled"; 1139 }; 1140 1141 i2s1: i2s@fc04c000 { 1142 compatible = "atmel,sama5d2-i2s"; 1143 reg = <0xfc04c000 0x100>; 1144 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1145 dmas = <&dma0 1146 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1147 AT91_XDMAC_DT_PERID(33))>, 1148 <&dma0 1149 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1150 AT91_XDMAC_DT_PERID(34))>; 1151 dma-names = "tx", "rx"; 1152 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1153 clock-names = "pclk", "gclk"; 1154 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1155 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1156 status = "disabled"; 1157 }; 1158 1159 can1: can@fc050000 { 1160 compatible = "bosch,m_can"; 1161 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1162 reg-names = "m_can", "message_ram"; 1163 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1164 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1165 interrupt-names = "int0", "int1"; 1166 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1167 clock-names = "hclk", "cclk"; 1168 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1169 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1170 assigned-clock-rates = <40000000>; 1171 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1172 status = "disabled"; 1173 }; 1174 1175 sfrbu: sfr@fc05c000 { 1176 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1177 reg = <0xfc05c000 0x20>; 1178 }; 1179 1180 chipid@fc069000 { 1181 compatible = "atmel,sama5d2-chipid"; 1182 reg = <0xfc069000 0x8>; 1183 }; 1184 }; 1185 }; 1186}; 1187