1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9#include <dt-bindings/dma/at91.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/clock/at91.h> 12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Atmel SAMA5D2 family SoC"; 18 compatible = "atmel,sama5d2"; 19 interrupt-parent = <&aic>; 20 21 aliases { 22 serial0 = &uart1; 23 serial1 = &uart3; 24 }; 25 26 cpus { 27 #address-cells = <1>; 28 #size-cells = <0>; 29 30 cpu@0 { 31 device_type = "cpu"; 32 compatible = "arm,cortex-a5"; 33 reg = <0>; 34 next-level-cache = <&L2>; 35 clocks = <&pmc PMC_TYPE_CORE PMC_MCK_PRES>; 36 clock-names = "cpu"; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a5-pmu"; 42 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; 43 }; 44 45 etb@740000 { 46 compatible = "arm,coresight-etb10", "arm,primecell"; 47 reg = <0x740000 0x1000>; 48 49 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 50 clock-names = "apb_pclk"; 51 52 in-ports { 53 port { 54 etb_in: endpoint { 55 remote-endpoint = <&etm_out>; 56 }; 57 }; 58 }; 59 }; 60 61 etm@73c000 { 62 compatible = "arm,coresight-etm3x", "arm,primecell"; 63 reg = <0x73c000 0x1000>; 64 65 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 66 clock-names = "apb_pclk"; 67 68 out-ports { 69 port { 70 etm_out: endpoint { 71 remote-endpoint = <&etb_in>; 72 }; 73 }; 74 }; 75 }; 76 77 memory@20000000 { 78 device_type = "memory"; 79 reg = <0x20000000 0x20000000>; 80 }; 81 82 clocks { 83 slow_xtal: slow_xtal { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <0>; 87 }; 88 89 main_xtal: main_xtal { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <0>; 93 }; 94 }; 95 96 ns_sram: sram@200000 { 97 compatible = "atmel,sama5d2-sram", "mmio-sram"; 98 reg = <0x00200000 0x20000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 ranges = <0 0x00200000 0x20000>; 102 status = "disabled"; 103 secure-status = "okay"; 104 }; 105 106 ahb { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges; 111 112 nfc_sram: sram@100000 { 113 compatible = "mmio-sram"; 114 no-memory-wc; 115 reg = <0x00100000 0x2400>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x00100000 0x2400>; 119 120 }; 121 122 usb0: gadget@300000 { 123 compatible = "atmel,sama5d3-udc"; 124 reg = <0x00300000 0x100000 125 0xfc02c000 0x400>; 126 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>; 127 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 128 clock-names = "pclk", "hclk"; 129 status = "disabled"; 130 }; 131 132 usb1: ohci@400000 { 133 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 134 reg = <0x00400000 0x100000>; 135 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 136 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>; 137 clock-names = "ohci_clk", "hclk", "uhpck"; 138 status = "disabled"; 139 }; 140 141 usb2: ehci@500000 { 142 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 143 reg = <0x00500000 0x100000>; 144 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; 145 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>; 146 clock-names = "usb_clk", "ehci_clk"; 147 status = "disabled"; 148 }; 149 150 L2: cache-controller@a00000 { 151 compatible = "arm,pl310-cache"; 152 reg = <0x00a00000 0x1000>; 153 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>; 154 cache-unified; 155 cache-level = <2>; 156 }; 157 158 ebi: ebi@10000000 { 159 compatible = "atmel,sama5d3-ebi"; 160 #address-cells = <2>; 161 #size-cells = <1>; 162 atmel,smc = <&hsmc>; 163 reg = <0x10000000 0x10000000 164 0x60000000 0x30000000>; 165 ranges = <0x0 0x0 0x10000000 0x10000000 166 0x1 0x0 0x60000000 0x10000000 167 0x2 0x0 0x70000000 0x10000000 168 0x3 0x0 0x80000000 0x10000000>; 169 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 170 status = "disabled"; 171 172 nand_controller: nand-controller { 173 compatible = "atmel,sama5d3-nand-controller"; 174 atmel,nfc-sram = <&nfc_sram>; 175 atmel,nfc-io = <&nfc_io>; 176 ecc-engine = <&pmecc>; 177 #address-cells = <2>; 178 #size-cells = <1>; 179 ranges; 180 status = "disabled"; 181 }; 182 }; 183 184 sdmmc0: sdio-host@a0000000 { 185 compatible = "atmel,sama5d2-sdhci"; 186 reg = <0xa0000000 0x300>; 187 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; 188 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 189 clock-names = "hclock", "multclk", "baseclk"; 190 assigned-clocks = <&pmc PMC_TYPE_GCK 31>; 191 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 192 assigned-clock-rates = <480000000>; 193 status = "disabled"; 194 }; 195 196 sdmmc1: sdio-host@b0000000 { 197 compatible = "atmel,sama5d2-sdhci"; 198 reg = <0xb0000000 0x300>; 199 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>; 200 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>; 201 clock-names = "hclock", "multclk", "baseclk"; 202 assigned-clocks = <&pmc PMC_TYPE_GCK 32>; 203 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 204 assigned-clock-rates = <480000000>; 205 status = "disabled"; 206 }; 207 208 nfc_io: nfc-io@c0000000 { 209 compatible = "atmel,sama5d3-nfc-io", "syscon"; 210 reg = <0xc0000000 0x8000000>; 211 }; 212 213 apb { 214 compatible = "simple-bus"; 215 #address-cells = <1>; 216 #size-cells = <1>; 217 ranges; 218 219 hlcdc: hlcdc@f0000000 { 220 compatible = "atmel,sama5d2-hlcdc"; 221 reg = <0xf0000000 0x2000>; 222 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 223 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 224 clock-names = "periph_clk","sys_clk", "slow_clk"; 225 status = "disabled"; 226 227 hlcdc-display-controller { 228 compatible = "atmel,hlcdc-display-controller"; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 232 port@0 { 233 #address-cells = <1>; 234 #size-cells = <0>; 235 reg = <0>; 236 }; 237 }; 238 239 hlcdc_pwm: hlcdc-pwm { 240 compatible = "atmel,hlcdc-pwm"; 241 #pwm-cells = <3>; 242 }; 243 }; 244 245 isc: isc@f0008000 { 246 compatible = "atmel,sama5d2-isc"; 247 reg = <0xf0008000 0x4000>; 248 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>; 249 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>; 250 clock-names = "hclock", "iscck", "gck"; 251 #clock-cells = <0>; 252 clock-output-names = "isc-mck"; 253 status = "disabled"; 254 }; 255 256 ramc0: ramc@f000c000 { 257 compatible = "atmel,sama5d3-ddramc"; 258 reg = <0xf000c000 0x200>; 259 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>; 260 clock-names = "ddrck", "mpddr"; 261 }; 262 263 dma0: dma-controller@f0010000 { 264 compatible = "atmel,sama5d4-dma"; 265 reg = <0xf0010000 0x1000>; 266 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; 267 #dma-cells = <1>; 268 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 269 clock-names = "dma_clk"; 270 }; 271 272 /* Place dma1 here despite its address */ 273 dma1: dma-controller@f0004000 { 274 compatible = "atmel,sama5d4-dma"; 275 reg = <0xf0004000 0x1000>; 276 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>; 277 #dma-cells = <1>; 278 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 279 clock-names = "dma_clk"; 280 }; 281 282 pmc: pmc@f0014000 { 283 compatible = "atmel,sama5d2-pmc", "syscon"; 284 reg = <0xf0014000 0x160>; 285 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 286 #clock-cells = <2>; 287 clocks = <&clk32k>, <&main_xtal>; 288 clock-names = "slow_clk", "main_xtal"; 289 status = "disabled"; 290 secure-status = "okay"; 291 }; 292 293 qspi0: spi@f0020000 { 294 compatible = "atmel,sama5d2-qspi"; 295 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; 296 reg-names = "qspi_base", "qspi_mmap"; 297 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>; 298 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 qspi1: spi@f0024000 { 305 compatible = "atmel,sama5d2-qspi"; 306 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; 307 reg-names = "qspi_base", "qspi_mmap"; 308 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>; 309 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 sha@f0028000 { 316 compatible = "atmel,at91sam9g46-sha"; 317 reg = <0xf0028000 0x100>; 318 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 319 dmas = <&dma0 320 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 321 AT91_XDMAC_DT_PERID(30))>; 322 dma-names = "tx"; 323 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 324 clock-names = "sha_clk"; 325 status = "okay"; 326 }; 327 328 aes@f002c000 { 329 compatible = "atmel,at91sam9g46-aes"; 330 reg = <0xf002c000 0x100>; 331 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 332 dmas = <&dma0 333 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 334 AT91_XDMAC_DT_PERID(26))>, 335 <&dma0 336 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 337 AT91_XDMAC_DT_PERID(27))>; 338 dma-names = "tx", "rx"; 339 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 340 clock-names = "aes_clk"; 341 status = "okay"; 342 }; 343 344 spi0: spi@f8000000 { 345 compatible = "atmel,at91rm9200-spi"; 346 reg = <0xf8000000 0x100>; 347 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 348 dmas = <&dma0 349 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 350 AT91_XDMAC_DT_PERID(6))>, 351 <&dma0 352 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 353 AT91_XDMAC_DT_PERID(7))>; 354 dma-names = "tx", "rx"; 355 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 356 clock-names = "spi_clk"; 357 atmel,fifo-size = <16>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 status = "disabled"; 361 }; 362 363 ssc0: ssc@f8004000 { 364 compatible = "atmel,at91sam9g45-ssc"; 365 reg = <0xf8004000 0x4000>; 366 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 367 dmas = <&dma0 368 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 369 AT91_XDMAC_DT_PERID(21))>, 370 <&dma0 371 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 372 AT91_XDMAC_DT_PERID(22))>; 373 dma-names = "tx", "rx"; 374 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 375 clock-names = "pclk"; 376 status = "disabled"; 377 }; 378 379 macb0: ethernet@f8008000 { 380 compatible = "atmel,sama5d2-gem"; 381 reg = <0xf8008000 0x1000>; 382 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ 383 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ 384 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ 385 #address-cells = <1>; 386 #size-cells = <0>; 387 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; 388 clock-names = "hclk", "pclk"; 389 status = "disabled"; 390 }; 391 392 tcb0: timer@f800c000 { 393 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 reg = <0xf800c000 0x100>; 397 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 398 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>; 399 clock-names = "t0_clk", "gclk", "slow_clk"; 400 }; 401 402 tcb1: timer@f8010000 { 403 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 reg = <0xf8010000 0x100>; 407 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 408 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>; 409 clock-names = "t0_clk", "gclk", "slow_clk"; 410 status = "disabled"; 411 secure-status = "okay"; 412 }; 413 414 hsmc: hsmc@f8014000 { 415 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd"; 416 reg = <0xf8014000 0x1000>; 417 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>; 418 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>; 419 #address-cells = <1>; 420 #size-cells = <1>; 421 ranges; 422 423 pmecc: ecc-engine@f8014070 { 424 compatible = "atmel,sama5d2-pmecc"; 425 reg = <0xf8014070 0x490>, 426 <0xf8014500 0x100>; 427 }; 428 }; 429 430 pdmic: pdmic@f8018000 { 431 compatible = "atmel,sama5d2-pdmic"; 432 reg = <0xf8018000 0x124>; 433 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>; 434 dmas = <&dma0 435 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 436 | AT91_XDMAC_DT_PERID(50))>; 437 dma-names = "rx"; 438 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>; 439 clock-names = "pclk", "gclk"; 440 status = "disabled"; 441 }; 442 443 uart0: serial@f801c000 { 444 compatible = "atmel,at91sam9260-usart"; 445 reg = <0xf801c000 0x100>; 446 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>; 447 dmas = <&dma0 448 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 449 AT91_XDMAC_DT_PERID(35))>, 450 <&dma0 451 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 452 AT91_XDMAC_DT_PERID(36))>; 453 dma-names = "tx", "rx"; 454 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 455 clock-names = "usart"; 456 status = "disabled"; 457 }; 458 459 uart1: serial@f8020000 { 460 compatible = "atmel,at91sam9260-usart"; 461 reg = <0xf8020000 0x100>; 462 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>; 463 dmas = <&dma0 464 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 465 AT91_XDMAC_DT_PERID(37))>, 466 <&dma0 467 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 468 AT91_XDMAC_DT_PERID(38))>; 469 dma-names = "tx", "rx"; 470 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 471 clock-names = "usart"; 472 status = "disabled"; 473 }; 474 475 uart2: serial@f8024000 { 476 compatible = "atmel,at91sam9260-usart"; 477 reg = <0xf8024000 0x100>; 478 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>; 479 dmas = <&dma0 480 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 481 AT91_XDMAC_DT_PERID(39))>, 482 <&dma0 483 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 484 AT91_XDMAC_DT_PERID(40))>; 485 dma-names = "tx", "rx"; 486 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 487 clock-names = "usart"; 488 status = "disabled"; 489 }; 490 491 i2c0: i2c@f8028000 { 492 compatible = "atmel,sama5d2-i2c"; 493 reg = <0xf8028000 0x100>; 494 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>; 495 dmas = <&dma0 496 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 497 AT91_XDMAC_DT_PERID(0))>, 498 <&dma0 499 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 500 AT91_XDMAC_DT_PERID(1))>; 501 dma-names = "tx", "rx"; 502 #address-cells = <1>; 503 #size-cells = <0>; 504 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 505 atmel,fifo-size = <16>; 506 status = "disabled"; 507 }; 508 509 pwm0: pwm@f802c000 { 510 compatible = "atmel,sama5d2-pwm"; 511 reg = <0xf802c000 0x4000>; 512 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>; 513 #pwm-cells = <3>; 514 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 515 status = "disabled"; 516 }; 517 518 sfr: sfr@f8030000 { 519 compatible = "atmel,sama5d2-sfr", "syscon"; 520 reg = <0xf8030000 0x98>; 521 status = "disabled"; 522 secure-status = "okay"; 523 }; 524 525 flx0: flexcom@f8034000 { 526 compatible = "atmel,sama5d2-flexcom"; 527 reg = <0xf8034000 0x200>; 528 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 529 #address-cells = <1>; 530 #size-cells = <1>; 531 ranges = <0x0 0xf8034000 0x800>; 532 status = "disabled"; 533 534 uart5: serial@200 { 535 compatible = "atmel,at91sam9260-usart"; 536 reg = <0x200 0x200>; 537 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 538 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 539 clock-names = "usart"; 540 dmas = <&dma0 541 (AT91_XDMAC_DT_MEM_IF(0) | 542 AT91_XDMAC_DT_PER_IF(1) | 543 AT91_XDMAC_DT_PERID(11))>, 544 <&dma0 545 (AT91_XDMAC_DT_MEM_IF(0) | 546 AT91_XDMAC_DT_PER_IF(1) | 547 AT91_XDMAC_DT_PERID(12))>; 548 dma-names = "tx", "rx"; 549 atmel,fifo-size = <32>; 550 status = "disabled"; 551 }; 552 553 spi2: spi@400 { 554 compatible = "atmel,at91rm9200-spi"; 555 reg = <0x400 0x200>; 556 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 560 clock-names = "spi_clk"; 561 dmas = <&dma0 562 (AT91_XDMAC_DT_MEM_IF(0) | 563 AT91_XDMAC_DT_PER_IF(1) | 564 AT91_XDMAC_DT_PERID(11))>, 565 <&dma0 566 (AT91_XDMAC_DT_MEM_IF(0) | 567 AT91_XDMAC_DT_PER_IF(1) | 568 AT91_XDMAC_DT_PERID(12))>; 569 dma-names = "tx", "rx"; 570 atmel,fifo-size = <16>; 571 status = "disabled"; 572 }; 573 574 i2c2: i2c@600 { 575 compatible = "atmel,sama5d2-i2c"; 576 reg = <0x600 0x200>; 577 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 581 dmas = <&dma0 582 (AT91_XDMAC_DT_MEM_IF(0) | 583 AT91_XDMAC_DT_PER_IF(1) | 584 AT91_XDMAC_DT_PERID(11))>, 585 <&dma0 586 (AT91_XDMAC_DT_MEM_IF(0) | 587 AT91_XDMAC_DT_PER_IF(1) | 588 AT91_XDMAC_DT_PERID(12))>; 589 dma-names = "tx", "rx"; 590 atmel,fifo-size = <16>; 591 status = "disabled"; 592 }; 593 }; 594 595 flx1: flexcom@f8038000 { 596 compatible = "atmel,sama5d2-flexcom"; 597 reg = <0xf8038000 0x200>; 598 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 599 #address-cells = <1>; 600 #size-cells = <1>; 601 ranges = <0x0 0xf8038000 0x800>; 602 status = "disabled"; 603 604 uart6: serial@200 { 605 compatible = "atmel,at91sam9260-usart"; 606 reg = <0x200 0x200>; 607 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 608 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 609 clock-names = "usart"; 610 dmas = <&dma0 611 (AT91_XDMAC_DT_MEM_IF(0) | 612 AT91_XDMAC_DT_PER_IF(1) | 613 AT91_XDMAC_DT_PERID(13))>, 614 <&dma0 615 (AT91_XDMAC_DT_MEM_IF(0) | 616 AT91_XDMAC_DT_PER_IF(1) | 617 AT91_XDMAC_DT_PERID(14))>; 618 dma-names = "tx", "rx"; 619 atmel,fifo-size = <32>; 620 status = "disabled"; 621 }; 622 623 spi3: spi@400 { 624 compatible = "atmel,at91rm9200-spi"; 625 reg = <0x400 0x200>; 626 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 630 clock-names = "spi_clk"; 631 dmas = <&dma0 632 (AT91_XDMAC_DT_MEM_IF(0) | 633 AT91_XDMAC_DT_PER_IF(1) | 634 AT91_XDMAC_DT_PERID(13))>, 635 <&dma0 636 (AT91_XDMAC_DT_MEM_IF(0) | 637 AT91_XDMAC_DT_PER_IF(1) | 638 AT91_XDMAC_DT_PERID(14))>; 639 dma-names = "tx", "rx"; 640 atmel,fifo-size = <16>; 641 status = "disabled"; 642 }; 643 644 i2c3: i2c@600 { 645 compatible = "atmel,sama5d2-i2c"; 646 reg = <0x600 0x200>; 647 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>; 648 #address-cells = <1>; 649 #size-cells = <0>; 650 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 651 dmas = <&dma0 652 (AT91_XDMAC_DT_MEM_IF(0) | 653 AT91_XDMAC_DT_PER_IF(1) | 654 AT91_XDMAC_DT_PERID(13))>, 655 <&dma0 656 (AT91_XDMAC_DT_MEM_IF(0) | 657 AT91_XDMAC_DT_PER_IF(1) | 658 AT91_XDMAC_DT_PERID(14))>; 659 dma-names = "tx", "rx"; 660 atmel,fifo-size = <16>; 661 status = "disabled"; 662 }; 663 }; 664 665 securam: sram@f8044000 { 666 compatible = "atmel,sama5d2-securam", "mmio-sram"; 667 reg = <0xf8044000 0x1420>; 668 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>; 669 #address-cells = <1>; 670 #size-cells = <1>; 671 no-memory-wc; 672 ranges = <0 0xf8044000 0x1420>; 673 status = "disabled"; 674 secure-status = "okay"; 675 }; 676 677 reset_controller: rstc@f8048000 { 678 compatible = "atmel,sama5d3-rstc"; 679 reg = <0xf8048000 0x10>; 680 clocks = <&clk32k>; 681 }; 682 683 shutdown_controller: shdwc@f8048010 { 684 compatible = "atmel,sama5d2-shdwc"; 685 reg = <0xf8048010 0x10>; 686 clocks = <&clk32k>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 atmel,wakeup-rtc-timer; 690 }; 691 692 pit: timer@f8048030 { 693 compatible = "atmel,at91sam9260-pit"; 694 reg = <0xf8048030 0x10>; 695 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 696 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 697 }; 698 699 watchdog: watchdog@f8048040 { 700 compatible = "atmel,sama5d4-wdt"; 701 reg = <0xf8048040 0x10>; 702 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 703 clocks = <&clk32k>; 704 status = "disabled"; 705 secure-status = "okay"; 706 }; 707 708 clk32k: sckc@f8048050 { 709 compatible = "atmel,sama5d4-sckc"; 710 reg = <0xf8048050 0x4>; 711 712 clocks = <&slow_xtal>; 713 #clock-cells = <0>; 714 }; 715 716 rtc: rtc@f80480b0 { 717 compatible = "atmel,sama5d2-rtc"; 718 reg = <0xf80480b0 0x30>; 719 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>; 720 clocks = <&clk32k>; 721 status = "disabled"; 722 secure-status = "okay"; 723 }; 724 725 i2s0: i2s@f8050000 { 726 compatible = "atmel,sama5d2-i2s"; 727 reg = <0xf8050000 0x100>; 728 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>; 729 dmas = <&dma0 730 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 731 AT91_XDMAC_DT_PERID(31))>, 732 <&dma0 733 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 734 AT91_XDMAC_DT_PERID(32))>; 735 dma-names = "tx", "rx"; 736 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>; 737 clock-names = "pclk", "gclk"; 738 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>; 739 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>; 740 status = "disabled"; 741 }; 742 743 can0: can@f8054000 { 744 compatible = "bosch,m_can"; 745 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>; 746 reg-names = "m_can", "message_ram"; 747 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>, 748 <64 IRQ_TYPE_LEVEL_HIGH 7>; 749 interrupt-names = "int0", "int1"; 750 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>; 751 clock-names = "hclk", "cclk"; 752 assigned-clocks = <&pmc PMC_TYPE_GCK 56>; 753 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 754 assigned-clock-rates = <40000000>; 755 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>; 756 status = "disabled"; 757 }; 758 759 spi1: spi@fc000000 { 760 compatible = "atmel,at91rm9200-spi"; 761 reg = <0xfc000000 0x100>; 762 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 763 dmas = <&dma0 764 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 765 AT91_XDMAC_DT_PERID(8))>, 766 <&dma0 767 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 768 AT91_XDMAC_DT_PERID(9))>; 769 dma-names = "tx", "rx"; 770 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 771 clock-names = "spi_clk"; 772 atmel,fifo-size = <16>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 uart3: serial@fc008000 { 779 compatible = "atmel,at91sam9260-usart"; 780 reg = <0xfc008000 0x100>; 781 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>; 782 dmas = <&dma1 783 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 784 AT91_XDMAC_DT_PERID(41))>, 785 <&dma1 786 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 787 AT91_XDMAC_DT_PERID(42))>; 788 dma-names = "tx", "rx"; 789 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 790 clock-names = "usart"; 791 status = "disabled"; 792 }; 793 794 uart4: serial@fc00c000 { 795 compatible = "atmel,at91sam9260-usart"; 796 reg = <0xfc00c000 0x100>; 797 dmas = <&dma0 798 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 799 AT91_XDMAC_DT_PERID(43))>, 800 <&dma0 801 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 802 AT91_XDMAC_DT_PERID(44))>; 803 dma-names = "tx", "rx"; 804 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>; 805 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 806 clock-names = "usart"; 807 status = "disabled"; 808 }; 809 810 flx2: flexcom@fc010000 { 811 compatible = "atmel,sama5d2-flexcom"; 812 reg = <0xfc010000 0x200>; 813 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 ranges = <0x0 0xfc010000 0x800>; 817 status = "disabled"; 818 819 uart7: serial@200 { 820 compatible = "atmel,at91sam9260-usart"; 821 reg = <0x200 0x200>; 822 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 823 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 824 clock-names = "usart"; 825 dmas = <&dma0 826 (AT91_XDMAC_DT_MEM_IF(0) | 827 AT91_XDMAC_DT_PER_IF(1) | 828 AT91_XDMAC_DT_PERID(15))>, 829 <&dma0 830 (AT91_XDMAC_DT_MEM_IF(0) | 831 AT91_XDMAC_DT_PER_IF(1) | 832 AT91_XDMAC_DT_PERID(16))>; 833 dma-names = "tx", "rx"; 834 atmel,fifo-size = <32>; 835 status = "disabled"; 836 }; 837 838 spi4: spi@400 { 839 compatible = "atmel,at91rm9200-spi"; 840 reg = <0x400 0x200>; 841 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 845 clock-names = "spi_clk"; 846 dmas = <&dma0 847 (AT91_XDMAC_DT_MEM_IF(0) | 848 AT91_XDMAC_DT_PER_IF(1) | 849 AT91_XDMAC_DT_PERID(15))>, 850 <&dma0 851 (AT91_XDMAC_DT_MEM_IF(0) | 852 AT91_XDMAC_DT_PER_IF(1) | 853 AT91_XDMAC_DT_PERID(16))>; 854 dma-names = "tx", "rx"; 855 atmel,fifo-size = <16>; 856 status = "disabled"; 857 }; 858 859 i2c4: i2c@600 { 860 compatible = "atmel,sama5d2-i2c"; 861 reg = <0x600 0x200>; 862 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; 866 dmas = <&dma0 867 (AT91_XDMAC_DT_MEM_IF(0) | 868 AT91_XDMAC_DT_PER_IF(1) | 869 AT91_XDMAC_DT_PERID(15))>, 870 <&dma0 871 (AT91_XDMAC_DT_MEM_IF(0) | 872 AT91_XDMAC_DT_PER_IF(1) | 873 AT91_XDMAC_DT_PERID(16))>; 874 dma-names = "tx", "rx"; 875 atmel,fifo-size = <16>; 876 status = "disabled"; 877 }; 878 }; 879 880 flx3: flexcom@fc014000 { 881 compatible = "atmel,sama5d2-flexcom"; 882 reg = <0xfc014000 0x200>; 883 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 884 #address-cells = <1>; 885 #size-cells = <1>; 886 ranges = <0x0 0xfc014000 0x800>; 887 status = "disabled"; 888 889 uart8: serial@200 { 890 compatible = "atmel,at91sam9260-usart"; 891 reg = <0x200 0x200>; 892 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 893 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 894 clock-names = "usart"; 895 dmas = <&dma0 896 (AT91_XDMAC_DT_MEM_IF(0) | 897 AT91_XDMAC_DT_PER_IF(1) | 898 AT91_XDMAC_DT_PERID(17))>, 899 <&dma0 900 (AT91_XDMAC_DT_MEM_IF(0) | 901 AT91_XDMAC_DT_PER_IF(1) | 902 AT91_XDMAC_DT_PERID(18))>; 903 dma-names = "tx", "rx"; 904 atmel,fifo-size = <32>; 905 status = "disabled"; 906 }; 907 908 spi5: spi@400 { 909 compatible = "atmel,at91rm9200-spi"; 910 reg = <0x400 0x200>; 911 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 915 clock-names = "spi_clk"; 916 dmas = <&dma0 917 (AT91_XDMAC_DT_MEM_IF(0) | 918 AT91_XDMAC_DT_PER_IF(1) | 919 AT91_XDMAC_DT_PERID(17))>, 920 <&dma0 921 (AT91_XDMAC_DT_MEM_IF(0) | 922 AT91_XDMAC_DT_PER_IF(1) | 923 AT91_XDMAC_DT_PERID(18))>; 924 dma-names = "tx", "rx"; 925 atmel,fifo-size = <16>; 926 status = "disabled"; 927 }; 928 929 i2c5: i2c@600 { 930 compatible = "atmel,sama5d2-i2c"; 931 reg = <0x600 0x200>; 932 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 936 dmas = <&dma0 937 (AT91_XDMAC_DT_MEM_IF(0) | 938 AT91_XDMAC_DT_PER_IF(1) | 939 AT91_XDMAC_DT_PERID(17))>, 940 <&dma0 941 (AT91_XDMAC_DT_MEM_IF(0) | 942 AT91_XDMAC_DT_PER_IF(1) | 943 AT91_XDMAC_DT_PERID(18))>; 944 dma-names = "tx", "rx"; 945 atmel,fifo-size = <16>; 946 status = "disabled"; 947 }; 948 949 }; 950 951 flx4: flexcom@fc018000 { 952 compatible = "atmel,sama5d2-flexcom"; 953 reg = <0xfc018000 0x200>; 954 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 955 #address-cells = <1>; 956 #size-cells = <1>; 957 ranges = <0x0 0xfc018000 0x800>; 958 status = "disabled"; 959 960 uart9: serial@200 { 961 compatible = "atmel,at91sam9260-usart"; 962 reg = <0x200 0x200>; 963 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 964 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 965 clock-names = "usart"; 966 dmas = <&dma0 967 (AT91_XDMAC_DT_MEM_IF(0) | 968 AT91_XDMAC_DT_PER_IF(1) | 969 AT91_XDMAC_DT_PERID(19))>, 970 <&dma0 971 (AT91_XDMAC_DT_MEM_IF(0) | 972 AT91_XDMAC_DT_PER_IF(1) | 973 AT91_XDMAC_DT_PERID(20))>; 974 dma-names = "tx", "rx"; 975 atmel,fifo-size = <32>; 976 status = "disabled"; 977 }; 978 979 spi6: spi@400 { 980 compatible = "atmel,at91rm9200-spi"; 981 reg = <0x400 0x200>; 982 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 986 clock-names = "spi_clk"; 987 dmas = <&dma0 988 (AT91_XDMAC_DT_MEM_IF(0) | 989 AT91_XDMAC_DT_PER_IF(1) | 990 AT91_XDMAC_DT_PERID(19))>, 991 <&dma0 992 (AT91_XDMAC_DT_MEM_IF(0) | 993 AT91_XDMAC_DT_PER_IF(1) | 994 AT91_XDMAC_DT_PERID(20))>; 995 dma-names = "tx", "rx"; 996 atmel,fifo-size = <16>; 997 status = "disabled"; 998 }; 999 1000 i2c6: i2c@600 { 1001 compatible = "atmel,sama5d2-i2c"; 1002 reg = <0x600 0x200>; 1003 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 1007 dmas = <&dma0 1008 (AT91_XDMAC_DT_MEM_IF(0) | 1009 AT91_XDMAC_DT_PER_IF(1) | 1010 AT91_XDMAC_DT_PERID(19))>, 1011 <&dma0 1012 (AT91_XDMAC_DT_MEM_IF(0) | 1013 AT91_XDMAC_DT_PER_IF(1) | 1014 AT91_XDMAC_DT_PERID(20))>; 1015 dma-names = "tx", "rx"; 1016 atmel,fifo-size = <16>; 1017 status = "disabled"; 1018 }; 1019 }; 1020 1021 trng@fc01c000 { 1022 compatible = "atmel,at91sam9g45-trng"; 1023 reg = <0xfc01c000 0x100>; 1024 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; 1025 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1026 status = "disabled"; 1027 secure-status = "okay"; 1028 }; 1029 1030 aic: interrupt-controller@fc020000 { 1031 #interrupt-cells = <3>; 1032 compatible = "atmel,sama5d2-aic"; 1033 interrupt-controller; 1034 reg = <0xfc020000 0x200>; 1035 atmel,external-irqs = <49>; 1036 }; 1037 1038 saic: interrupt-controller@f803c000 { 1039 #interrupt-cells = <3>; 1040 compatible = "atmel,sama5d2-saic"; 1041 interrupt-controller; 1042 reg = <0xf803c000 0x200>; 1043 atmel,external-irqs = <49>; 1044 status = "disabled"; 1045 secure-status = "okay"; 1046 }; 1047 1048 i2c1: i2c@fc028000 { 1049 compatible = "atmel,sama5d2-i2c"; 1050 reg = <0xfc028000 0x100>; 1051 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>; 1052 dmas = <&dma0 1053 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1054 AT91_XDMAC_DT_PERID(2))>, 1055 <&dma0 1056 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1057 AT91_XDMAC_DT_PERID(3))>; 1058 dma-names = "tx", "rx"; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 1062 atmel,fifo-size = <16>; 1063 status = "disabled"; 1064 }; 1065 1066 adc: adc@fc030000 { 1067 compatible = "atmel,sama5d2-adc"; 1068 reg = <0xfc030000 0x100>; 1069 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>; 1070 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 1071 clock-names = "adc_clk"; 1072 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>; 1073 dma-names = "rx"; 1074 atmel,min-sample-rate-hz = <200000>; 1075 atmel,max-sample-rate-hz = <20000000>; 1076 atmel,startup-time-ms = <4>; 1077 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1078 #io-channel-cells = <1>; 1079 status = "disabled"; 1080 }; 1081 1082 resistive_touch: resistive-touch { 1083 compatible = "resistive-adc-touch"; 1084 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>, 1085 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>, 1086 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>; 1087 io-channel-names = "x", "y", "pressure"; 1088 touchscreen-min-pressure = <50000>; 1089 status = "disabled"; 1090 }; 1091 1092 pioA: pinctrl@fc038000 { 1093 compatible = "atmel,sama5d2-pinctrl"; 1094 reg = <0xfc038000 0x600>; 1095 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, 1096 <68 IRQ_TYPE_LEVEL_HIGH 7>, 1097 <69 IRQ_TYPE_LEVEL_HIGH 7>, 1098 <70 IRQ_TYPE_LEVEL_HIGH 7>; 1099 interrupt-controller; 1100 #interrupt-cells = <2>; 1101 gpio-controller; 1102 #gpio-cells = <2>; 1103 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1104 }; 1105 1106 pioBU: secumod@fc040000 { 1107 compatible = "atmel,sama5d2-secumod", "syscon"; 1108 reg = <0xfc040000 0x100>; 1109 1110 gpio-controller; 1111 #gpio-cells = <2>; 1112 status = "disabled"; 1113 secure-status = "okay"; 1114 }; 1115 1116 tdes@fc044000 { 1117 compatible = "atmel,at91sam9g46-tdes"; 1118 reg = <0xfc044000 0x100>; 1119 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 1120 dmas = <&dma0 1121 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1122 AT91_XDMAC_DT_PERID(28))>, 1123 <&dma0 1124 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1125 AT91_XDMAC_DT_PERID(29))>; 1126 dma-names = "tx", "rx"; 1127 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 1128 clock-names = "tdes_clk"; 1129 status = "okay"; 1130 }; 1131 1132 classd: classd@fc048000 { 1133 compatible = "atmel,sama5d2-classd"; 1134 reg = <0xfc048000 0x100>; 1135 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>; 1136 dmas = <&dma0 1137 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1138 AT91_XDMAC_DT_PERID(47))>; 1139 dma-names = "tx"; 1140 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>; 1141 clock-names = "pclk", "gclk"; 1142 status = "disabled"; 1143 }; 1144 1145 i2s1: i2s@fc04c000 { 1146 compatible = "atmel,sama5d2-i2s"; 1147 reg = <0xfc04c000 0x100>; 1148 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>; 1149 dmas = <&dma0 1150 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1151 AT91_XDMAC_DT_PERID(33))>, 1152 <&dma0 1153 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1154 AT91_XDMAC_DT_PERID(34))>; 1155 dma-names = "tx", "rx"; 1156 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>; 1157 clock-names = "pclk", "gclk"; 1158 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>; 1159 assigned-parrents = <&pmc PMC_TYPE_GCK 55>; 1160 status = "disabled"; 1161 }; 1162 1163 can1: can@fc050000 { 1164 compatible = "bosch,m_can"; 1165 reg = <0xfc050000 0x4000>, <0x210000 0x3800>; 1166 reg-names = "m_can", "message_ram"; 1167 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>, 1168 <65 IRQ_TYPE_LEVEL_HIGH 7>; 1169 interrupt-names = "int0", "int1"; 1170 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>; 1171 clock-names = "hclk", "cclk"; 1172 assigned-clocks = <&pmc PMC_TYPE_GCK 57>; 1173 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>; 1174 assigned-clock-rates = <40000000>; 1175 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>; 1176 status = "disabled"; 1177 }; 1178 1179 sfrbu: sfr@fc05c000 { 1180 compatible = "atmel,sama5d2-sfrbu", "syscon"; 1181 reg = <0xfc05c000 0x20>; 1182 }; 1183 1184 chipid@fc069000 { 1185 compatible = "atmel,sama5d2-chipid"; 1186 reg = <0xfc069000 0x8>; 1187 }; 1188 }; 1189 }; 1190}; 1191